[OEM-5.6][PATCH 10/37] drm/i915/tgl: Program MBUS_ABOX{1, 2}_CTL during display init
Timo Aaltonen
tjaalton at ubuntu.com
Tue Mar 24 14:32:39 UTC 2020
From: Matt Roper <matthew.d.roper at intel.com>
BugLink: https://bugs.launchpad.net/bugs/1868727
On gen11 we only needed to program MBus credits into MBUS_ABOX_CTL
during display initialization, but on gen12 we're now supposed to
program the same values into MBUS_ABOX1_CTL and MBUS_ABOX2_CTL as well.
v2:
- Program registers with rmw to preserve contents of unrelated bits.
- Switch to the new display uncore helpers.
Bspec: 49213
Bspec: 50096
Cc: Stanislav Lisovskiy <stanislav.lisovskiy at intel.com>
Signed-off-by: Matt Roper <matthew.d.roper at intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20200204011032.582737-2-matthew.d.roper@intel.com
Reviewed-by: Matt Atwood <matthew.s.atwood at intel.com>
(backported from drm-intel-next commit 1042b2b93dac8029122fa7abeedf6b8f0f795a25)
Signed-off-by: Timo Aaltonen <timo.aaltonen at canonical.com>
---
drivers/gpu/drm/i915/display/intel_display_power.c | 4 ++++
drivers/gpu/drm/i915/i915_reg.h | 2 ++
2 files changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index 46c40db992dd..e819686ed547 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -4480,6 +4480,10 @@ static void icl_mbus_init(struct drm_i915_private *dev_priv)
MBUS_ABOX_B_CREDIT(1) |
MBUS_ABOX_BW_CREDIT(1);
I915_WRITE(MBUS_ABOX_CTL, val);
+ if (INTEL_GEN(dev_priv) >= 12) {
+ I915_WRITE(MBUS_ABOX1_CTL, val);
+ I915_WRITE(MBUS_ABOX2_CTL, val);
+ }
}
static void hsw_assert_cdclk(struct drm_i915_private *dev_priv)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 1a2929a4d70a..41c538522dad 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2860,6 +2860,8 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
#define MI_ARB_STATE _MMIO(0x20e4) /* 915+ only */
#define MBUS_ABOX_CTL _MMIO(0x45038)
+#define MBUS_ABOX1_CTL _MMIO(0x45048)
+#define MBUS_ABOX2_CTL _MMIO(0x4504C)
#define MBUS_ABOX_BW_CREDIT_MASK (3 << 20)
#define MBUS_ABOX_BW_CREDIT(x) ((x) << 20)
#define MBUS_ABOX_B_CREDIT_MASK (0xF << 16)
--
2.25.1
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