[Utopic][PATCH][Append 2/2] mmc: sdhci: Add a quirk for AMD SDHC transfer mode register need to be cleared for cmd without data
Adam Lee
adam.lee at canonical.com
Fri Sep 11 14:25:49 UTC 2015
From: Vincent Wan <vincent.wan at amd.com>
BugLink: https://bugs.launchpad.net/bugs/1472843
SDHC controller in AMD chipsets require SDHC transfer mode
register to be cleared for commands without data. The issue was
uncovered during testing eMMC cards on KB/ML based platforms
Signed-off-by: Vincent Wan <vincent.wan at amd.com>
Signed-off-by: Wan Zongshun <mcuos.com at gmail.com>
Signed-off-by: Arindam Nath <arindam.nath at amd.com>
Tested-by: Vikram B <vikram.b at amd.com>
Tested-by: Raghavendra Swamy <raghavendra.swamy at amd.com>
Signed-off-by: Ulf Hansson <ulf.hansson at linaro.org>
(back ported from commit 9b8ffea6efb0d0edcac265a1ca422188fc1b6dfb)
Signed-off-by: Adam Lee <adam.lee at canonical.com>
Conflicts:
include/linux/mmc/sdhci.h
---
drivers/mmc/host/sdhci.c | 9 +++++++--
include/linux/mmc/sdhci.h | 2 ++
2 files changed, 9 insertions(+), 2 deletions(-)
diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c
index 1d92337..d5d6362 100644
--- a/drivers/mmc/host/sdhci.c
+++ b/drivers/mmc/host/sdhci.c
@@ -880,10 +880,15 @@ static void sdhci_set_transfer_mode(struct sdhci_host *host,
struct mmc_data *data = cmd->data;
if (data == NULL) {
+ if (host->quirks2 &
+ SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD) {
+ sdhci_writew(host, 0x0, SDHCI_TRANSFER_MODE);
+ } else {
/* clear Auto CMD settings for no data CMDs */
- mode = sdhci_readw(host, SDHCI_TRANSFER_MODE);
- sdhci_writew(host, mode & ~(SDHCI_TRNS_AUTO_CMD12 |
+ mode = sdhci_readw(host, SDHCI_TRANSFER_MODE);
+ sdhci_writew(host, mode & ~(SDHCI_TRNS_AUTO_CMD12 |
SDHCI_TRNS_AUTO_CMD23), SDHCI_TRANSFER_MODE);
+ }
return;
}
diff --git a/include/linux/mmc/sdhci.h b/include/linux/mmc/sdhci.h
index 08abe99..e8b62fa 100644
--- a/include/linux/mmc/sdhci.h
+++ b/include/linux/mmc/sdhci.h
@@ -98,6 +98,8 @@ struct sdhci_host {
#define SDHCI_QUIRK2_BROKEN_HS200 (1<<6)
/* Controller does not support DDR50 */
#define SDHCI_QUIRK2_BROKEN_DDR50 (1<<7)
+/* need clear transfer mode register before send cmd */
+#define SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD (1<<10)
int irq; /* Device IRQ */
void __iomem *ioaddr; /* Mapped address */
--
2.5.1
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