[Bug 490371] Re: Atomic operations not safe for ARMv7, Thumb-2 and multicore

[Dave Martin]

The upstream commit looks at least semi-sane -- it looks like the memory
barrier stuff is merged in lp:ubuntu/qt4-x11, is my understanding
correct?

I also generally agree with upstream's view that they don't want to port
to the GCC primitives: since Qt already has a pretty decent atomics API,
and since the GCC atomics are crude by comparison, it probably doesn't
make sense to re-port Qt to the GCC atomics for the sake of it,
providing the code works.

I'm uncertain whether some of the "Ordered" primitives really are
ordered though:

Compare:

src/corelib/arch/qatomic_armv6.h:429:
inline bool QBasicAtomicInt::testAndSetOrdered(int expectedValue, int newValue)
{
    Q_DATA_MEMORY_BARRIER;
    bool returnValue = testAndSetRelaxed(expectedValue, newValue);
    Q_COMPILER_MEMORY_BARRIER;
    return returnValue;
}

src/corelib/arch/qatomic_armv6.h:495:
template <typename T>
Q_INLINE_TEMPLATE bool QBasicAtomicPointer<T>::testAndSetOrdered(T *expectedValue, T *newValue)
{
    Q_DATA_MEMORY_BARRIER;
    bool returnValue = testAndSetAcquire(expectedValue, newValue);
    Q_COMPILER_MEMORY_BARRIER;
    return returnValue;
}

In QBasicAtomicInt::testAndSetOrdered(int,int), I can't see why we don't
need Q_DATA_MEMORY_BARRIER after calling testAndSetRelaxed(); or
otherwise why we don't need to call testAndSetAcquire() to get that
barrier implicitly (as is done for
QBasicAtomicPointer<T>::testAndSetOrdered(T *,T *)).

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https://bugs.launchpad.net/bugs/490371

Title:
  Atomic operations not safe for ARMv7,Thumb-2 and multicore