<div dir="ltr"><div dir="ltr"><br></div><br><div class="gmail_quote"><div dir="ltr" class="gmail_attr">On Wed, Jul 21, 2021 at 3:21 PM Stefan Bader <<a href="mailto:stefan.bader@canonical.com">stefan.bader@canonical.com</a>> wrote:<br></div><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex">On 21.07.21 08:35, <a href="mailto:chris.chiu@canonical.com" target="_blank">chris.chiu@canonical.com</a> wrote:<br>
> From: Chris Chiu <<a href="mailto:chris.chiu@canonical.com" target="_blank">chris.chiu@canonical.com</a>><br>
> <br>
> BugLink: <a href="https://bugs.launchpad.net/bugs/1926579" rel="noreferrer" target="_blank">https://bugs.launchpad.net/bugs/1926579</a><br>
> <br>
> [Impact]<br>
> On Dell TGL platforms screen shows garbage when browsing website by scrolling mouse<br>
> <br>
> [Fix]<br>
> This patch fixes the issue<br>
> <a href="https://patchwork.freedesktop.org/patch/430153/?series=89348&rev=1" rel="noreferrer" target="_blank">https://patchwork.freedesktop.org/patch/430153/?series=89348&rev=1</a><br>
> It needs dependant commits on top of Hirsute base to access the stepping info to specifically disable PSR2 when stepping is B1 from A0.<br>
> <br>
> [Test]<br>
> Verified on Dell TGL-H platforms.<br>
> <br>
> [Where problems could occur]<br>
> It disable PSR2 on A0 and B0 TGL-H platforms, should introduce no regression.<br>
> <br>
> V2: Add more dependant patches to avoid as many conflicts as possible and add explanations for all backported section.<br>
> <br>
> Aditya Swarup (3):<br>
> drm/i915/tgl: Add bound checks and simplify TGL REVID macros<br>
> drm/i915/tgl: Use TGL stepping info for applying WAs<br>
> drm/i915/adl_s: Add display WAs for ADL-S<br>
> <br>
> Caz Yokoyama (1):<br>
> drm/i915/adl_s: Add ADL-S platform info and PCI ids<br>
> <br>
> Daniele Ceraolo Spurio (1):<br>
> drm/i915: split gen8+ flush and bb_start emission functions<br>
> <br>
> Gwan-gyeong Mun (1):<br>
> drm/i915/display: Disable PSR2 if TGL Display stepping is B1 from A0<br>
> <br>
> Jani Nikula (7):<br>
> drm/i915/pm: replace I915_READ()/WRITE() with<br>
> intel_uncore_read()/write()<br>
> drm/i915: remove unused ADLS_REVID_* macros<br>
> drm/i915: split out stepping info to a new file<br>
> drm/i915: add new helpers for accessing stepping info<br>
> drm/i915: switch KBL to the new stepping scheme<br>
> drm/i915: switch TGL and ADL to the new stepping scheme<br>
> drm/i915: rename DISP_STEPPING->DISPLAY_STEP and GT_STEPPING->GT_STEP<br>
> <br>
> John Harrison (1):<br>
> drm/i915: Correct location of Wa_1408615072<br>
> <br>
> Lucas De Marchi (3):<br>
> drm/i915: remove WA_SET_BIT_MASKED()<br>
> drm/i915: remove WA_CLR_BIT_MASKED()<br>
> drm/i915: remove WA_SET_FIELD_MASKED()<br>
> <br>
> Swathi Dhanavanthri (1):<br>
> drm/i915/dg1: Implement WA_16011163337<br>
> <br>
> drivers/gpu/drm/i915/Makefile | 2 +<br>
> .../drm/i915/display/intel_display_power.c | 9 +-<br>
> drivers/gpu/drm/i915/display/intel_psr.c | 11 +-<br>
> drivers/gpu/drm/i915/display/intel_sprite.c | 6 +-<br>
> drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 618 +++++++++++++++++<br>
> drivers/gpu/drm/i915/gt/gen8_engine_cs.h | 36 +<br>
> drivers/gpu/drm/i915/gt/intel_lrc.c | 629 +-----------------<br>
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 260 ++++----<br>
> drivers/gpu/drm/i915/i915_drv.c | 3 +-<br>
> drivers/gpu/drm/i915/i915_drv.h | 97 +--<br>
> drivers/gpu/drm/i915/i915_pci.c | 13 +<br>
> drivers/gpu/drm/i915/intel_device_info.c | 7 +-<br>
> drivers/gpu/drm/i915/intel_device_info.h | 5 +<br>
> drivers/gpu/drm/i915/intel_pm.c | 558 ++++++++--------<br>
> drivers/gpu/drm/i915/intel_step.c | 106 +++<br>
> drivers/gpu/drm/i915/intel_step.h | 40 ++<br>
> include/drm/i915_pciids.h | 11 +<br>
> 17 files changed, 1297 insertions(+), 1114 deletions(-)<br>
> create mode 100644 drivers/gpu/drm/i915/gt/gen8_engine_cs.c<br>
> create mode 100644 drivers/gpu/drm/i915/gt/gen8_engine_cs.h<br>
> create mode 100644 drivers/gpu/drm/i915/intel_step.c<br>
> create mode 100644 drivers/gpu/drm/i915/intel_step.h<br>
> <br>
Thanks for adding explanations. Though with a size like this, you should at <br>
least provide pull request style information in the cover email. This does not <br>
only simplify getting the set but also allows to look at things from various <br>
angles (as in show overall diff or individual patches).<br>
In my opinion SRU set should not strife for the least conflicts but for the <br>
least change. Only for LTS kernels there is the possible advantage to make <br>
future changes simpler. The kernels in between do not live that long. So there <br>
it is "the more one changes, the more one breaks". And as mentioned yesterday, <br>
the i915 driver breaks a lot. And it cannot be tested well. We don't have all <br>
the existing revisions of GPUs and even if we had, we could not have someone <br>
actually look at the screen.<br>
<br>
-Stefan<br>
<br>
<br></blockquote><div><br></div><div>Thanks for the clear explanations. I don't have to waste so much time and effort just for fixing conflicts and apply the same functions for old platforms. I'll propose a much simpler v3. </div></div></div>