[SRU][N/J:linux][PATCH 4/4] powerpc/bpf/64: Add instructions for atomic_[cmp]xchg

[Andrei Gherzan]

On Tue, 30 Jun 2026 at 17:58, Andrei Gherzan <andrei.gherzan at canonical.com>
wrote:

> BugLink: https://bugs.launchpad.net/bugs/1955011


Wrong subject series tag and missed the cover letter - scripts have failed.
I will send a v2.


>
>
> This adds two atomic opcodes BPF_XCHG and BPF_CMPXCHG on ppc64, both
> of which include the BPF_FETCH flag.  The kernel's atomic_cmpxchg
> operation fundamentally has 3 operands, but we only have two register
> fields. Therefore the operand we compare against (the kernel's API
> calls it 'old') is hard-coded to be BPF_REG_R0. Also, kernel's
> atomic_cmpxchg returns the previous value at dst_reg + off. JIT the
> same for BPF too with return value put in BPF_REG_0.
>
>   BPF_REG_R0 = atomic_cmpxchg(dst_reg + off, BPF_REG_R0, src_reg);
>
> This fixes the test_bpf.sh kernel selftest failure on PPC64 where 74 out
> of 577 BPF tests were failing with "FAIL to select_runtime err=-524" due
> to unsupported atomic operations.
>
> Signed-off-by: Hari Bathini <hbathini at linux.ibm.com>
> Tested-by: Naveen N. Rao <naveen.n.rao at linux.vnet.ibm.com> (ppc64le)
> Reviewed-by: Naveen N. Rao <naveen.n.rao at linux.vnet.ibm.com>
> Signed-off-by: Michael Ellerman <mpe at ellerman.id.au>
> Link:
> https://lore.kernel.org/r/20220610155552.25892-4-hbathini@linux.ibm.com
> (backported from commit 1e82dfaa7819f03f0b0022be7ca15bbc83090da1)
> [agherzan: Context adjustment - used b2p[TMP_REG_x] and b2p[BPF_REG_0]
>  notation consistent with existing Ubuntu Jammy code instead of upstream's
>  tmp1_reg/tmp2_reg/bpf_to_ppc() local variables and functions. Added a
>  compound statement block to scope save_reg and ret_reg variables.]
> Signed-off-by: Andrei Gherzan <andrei.gherzan at canonical.com>
> ---
>  arch/powerpc/net/bpf_jit_comp64.c | 40 +++++++++++++++++++++++++++----
>  1 file changed, 35 insertions(+), 5 deletions(-)
>
> diff --git a/arch/powerpc/net/bpf_jit_comp64.c
> b/arch/powerpc/net/bpf_jit_comp64.c
> index 5c55bf41b03e..373218053ab8 100644
> --- a/arch/powerpc/net/bpf_jit_comp64.c
> +++ b/arch/powerpc/net/bpf_jit_comp64.c
> @@ -743,6 +743,10 @@ int bpf_jit_build_body(struct bpf_prog *fp, u32
> *image, struct codegen_context *
>                  */
>                 case BPF_STX | BPF_ATOMIC | BPF_W:
>                 case BPF_STX | BPF_ATOMIC | BPF_DW:
> +               {
> +                       u32 save_reg = b2p[TMP_REG_2];
> +                       u32 ret_reg = src_reg;
> +
>                         /* Get offset into TMP_REG_1 */
>                         EMIT(PPC_RAW_LI(b2p[TMP_REG_1], off));
>                         tmp_idx = ctx->idx * 4;
> @@ -773,6 +777,24 @@ int bpf_jit_build_body(struct bpf_prog *fp, u32
> *image, struct codegen_context *
>                         case BPF_XOR | BPF_FETCH:
>                                 EMIT(PPC_RAW_XOR(b2p[TMP_REG_2],
> b2p[TMP_REG_2], src_reg));
>                                 break;
> +                       case BPF_CMPXCHG:
> +                               /*
> +                                * Return old value in BPF_REG_0 for
> BPF_CMPXCHG &
> +                                * in src_reg for other cases.
> +                                */
> +                               ret_reg = b2p[BPF_REG_0];
> +
> +                               /* Compare with old value in BPF_R0 */
> +                               if (BPF_SIZE(code) == BPF_DW)
> +                                       EMIT(PPC_RAW_CMPD(b2p[BPF_REG_0],
> b2p[TMP_REG_2]));
> +                               else
> +                                       EMIT(PPC_RAW_CMPW(b2p[BPF_REG_0],
> b2p[TMP_REG_2]));
> +                               /* Don't set if different from old value */
> +                               PPC_BCC_SHORT(COND_NE, (ctx->idx + 3) * 4);
> +                               fallthrough;
> +                       case BPF_XCHG:
> +                               save_reg = src_reg;
> +                               break;
>                         default:
>                                 pr_err_ratelimited(
>                                         "eBPF filter atomic op code %02x
> (@%d) unsupported\n",
> @@ -782,16 +804,24 @@ int bpf_jit_build_body(struct bpf_prog *fp, u32
> *image, struct codegen_context *
>
>                         /* store new value */
>                         if (BPF_SIZE(code) == BPF_DW)
> -                               EMIT(PPC_RAW_STDCX(b2p[TMP_REG_2],
> b2p[TMP_REG_1], dst_reg));
> +                               EMIT(PPC_RAW_STDCX(save_reg,
> b2p[TMP_REG_1], dst_reg));
>                         else
> -                               EMIT(PPC_RAW_STWCX(b2p[TMP_REG_2],
> b2p[TMP_REG_1], dst_reg));
> +                               EMIT(PPC_RAW_STWCX(save_reg,
> b2p[TMP_REG_1], dst_reg));
>                         /* we're done if this succeeded */
>                         PPC_BCC_SHORT(COND_NE, tmp_idx);
>
> -                       /* For the BPF_FETCH variant, get old value into
> src_reg */
> -                       if (imm & BPF_FETCH)
> -                               EMIT(PPC_RAW_MR(src_reg, _R0));
> +                       if (imm & BPF_FETCH) {
> +                               EMIT(PPC_RAW_MR(ret_reg, _R0));
> +                               /*
> +                                * Skip unnecessary zero-extension for
> 32-bit cmpxchg.
> +                                * For context, see commit 39491867ace5.
> +                                */
> +                               if (BPF_SIZE(code) != BPF_DW && imm ==
> BPF_CMPXCHG &&
> +                                   insn_is_zext(&insn[i + 1]))
> +                                       addrs[++i] = ctx->idx * 4;
> +                       }
>                         break;
> +               }
>
>                 /*
>                  * BPF_LDX
> --
> 2.43.0
>
>

-- 
Andrei Gherzan
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