[SRU][R][PATCH 1/2] ASoC: SDCA: fix the register to ctl value conversion for Q7.8 format

[Chris Chiu]

From: Shuming Fan <shumingf at realtek.com>

BugLink: https://bugs.launchpad.net/bugs/2160200

The division calculation should be implemented using signed integer format.
This patch changes mc->shift from an unsigned type to a signed integer during the calculation.

Fixes: 501efdcb3b3a ("ASoC: SDCA: Pull the Q7.8 volume helpers out of soc-ops")
Signed-off-by: Shuming Fan <shumingf at realtek.com>
Reviewed-by: Charles Keepax <ckeepax at opensource.cirrus.com>
Link: https://patch.msgid.link/20260327082331.2277498-1-shumingf@realtek.com
Signed-off-by: Mark Brown <broonie at kernel.org>
(cherry picked from commit ae00200acb870ac00551350f26f03ced188bad6f)
Signed-off-by: Chris Chiu <chris.chiu at canonical.com>
---
 sound/soc/sdca/sdca_asoc.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/sound/soc/sdca/sdca_asoc.c b/sound/soc/sdca/sdca_asoc.c
index a342a4e56717..bc47b97fcb07 100644
--- a/sound/soc/sdca/sdca_asoc.c
+++ b/sound/soc/sdca/sdca_asoc.c
@@ -850,7 +850,7 @@ static int q78_read(struct snd_soc_component *component,
 
 	reg_val = snd_soc_component_read(component, reg);
 
-	val = (sign_extend32(reg_val, mc->sign_bit) / mc->shift) - mc->min;
+	val = (sign_extend32(reg_val, mc->sign_bit) / (int)mc->shift) - mc->min;
 
 	return val & GENMASK(mc->sign_bit, 0);
 }
-- 
2.43.0