[SRU][J][PATCH v2 17/20] tools headers x86 cpufeatures: Sync with the kernel sources to pick TDX, Zen, APIC MSR fence changes

[Juerg Haefliger]

From: Arnaldo Carvalho de Melo <acme at redhat.com>

To pick the changes from:

  1e536e10689700e0 ("x86/cpu: Detect TDX partial write machine check erratum")
  765a0542fdc7aad7 ("x86/virt/tdx: Detect TDX during kernel boot")
  30fa92832f405d5a ("x86/CPU/AMD: Add ZenX generations flags")
  04c3024560d3a14a ("x86/barrier: Do not serialize MSR accesses on AMD")

This causes these perf files to be rebuilt and brings some X86_FEATURE
that will be used when updating the copies of
tools/arch/x86/lib/mem{cpy,set}_64.S with the kernel sources:

      CC       /tmp/build/perf/bench/mem-memcpy-x86-64-asm.o
      CC       /tmp/build/perf/bench/mem-memset-x86-64-asm.o

And addresses this perf build warning:

  Warning: Kernel ABI header differences:
    diff -u tools/arch/x86/include/asm/cpufeatures.h arch/x86/include/asm/cpufeatures.h

Cc: Adrian Hunter <adrian.hunter at intel.com>
Cc: Borislav Petkov <bp at alien8.de>
Cc: Dave Hansen <dave.hansen at linux.intel.com>
Cc: Ian Rogers <irogers at google.com>
Cc: Jiri Olsa <jolsa at kernel.org>
Cc: Kai Huang <kai.huang at intel.com>
Cc: Namhyung Kim <namhyung at kernel.org>
Link: https://lore.kernel.org/lkml/
Signed-off-by: Arnaldo Carvalho de Melo <acme at redhat.com>
(backported from commit 15d6daad8f8add8ef99b6e4e2b5bf0db48e1a8db)
[juergh: Pick only X86_FEATURE_ZEN{2,3,4,1} defines.]
CVE-2024-53114
Signed-off-by: Juerg Haefliger <juerg.haefliger at canonical.com>
---
 tools/arch/x86/include/asm/cpufeatures.h | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/tools/arch/x86/include/asm/cpufeatures.h b/tools/arch/x86/include/asm/cpufeatures.h
index 9541c0ff941a..4b87e8cfab9f 100644
--- a/tools/arch/x86/include/asm/cpufeatures.h
+++ b/tools/arch/x86/include/asm/cpufeatures.h
@@ -301,6 +301,10 @@
 #define X86_FEATURE_RETHUNK		(11*32+14) /* "" Use REturn THUNK */
 #define X86_FEATURE_UNRET		(11*32+15) /* "" AMD BTB untrain return */
 #define X86_FEATURE_RSB_VMEXIT_LITE	(11*32+17) /* "" Fill RSB on VM-Exit when EIBRS is enabled */
+#define X86_FEATURE_ZEN2		(11*32+28) /* "" CPU based on Zen2 microarchitecture */
+#define X86_FEATURE_ZEN3		(11*32+29) /* "" CPU based on Zen3 microarchitecture */
+#define X86_FEATURE_ZEN4		(11*32+30) /* "" CPU based on Zen4 microarchitecture */
+#define X86_FEATURE_ZEN1		(11*32+31) /* "" CPU based on Zen1 microarchitecture */
 
 /* Intel-defined CPU features, CPUID level 0x00000007:1 (EAX), word 12 */
 #define X86_FEATURE_AVX_VNNI		(12*32+ 4) /* AVX VNNI instructions */
-- 
2.48.1