[SRU][J][PATCH v2 01/20] tools headers cpufeatures: Sync with the kernel sources

[Juerg Haefliger]

From: Arnaldo Carvalho de Melo <acme at redhat.com>

To pick the changes from:

  2b1299322016731d ("x86/speculation: Add RSB VM Exit protections")
  28a99e95f55c6185 ("x86/amd: Use IBPB for firmware calls")
  4ad3278df6fe2b08 ("x86/speculation: Disable RRSBA behavior")
  26aae8ccbc197223 ("x86/cpu/amd: Enumerate BTC_NO")
  9756bba28470722d ("x86/speculation: Fill RSB on vmexit for IBRS")
  3ebc170068885b6f ("x86/bugs: Add retbleed=ibpb")
  2dbb887e875b1de3 ("x86/entry: Add kernel IBRS implementation")
  6b80b59b35557065 ("x86/bugs: Report AMD retbleed vulnerability")
  a149180fbcf336e9 ("x86: Add magic AMD return-thunk")
  15e67227c49a5783 ("x86: Undo return-thunk damage")
  a883d624aed463c8 ("x86/cpufeatures: Move RETPOLINE flags to word 11")
  aae99a7c9ab371b2 ("x86/cpufeatures: Introduce x2AVIC CPUID bit")
  6f33a9daff9f0790 ("x86: Fix comment for X86_FEATURE_ZEN")
  51802186158c74a0 ("x86/speculation/mmio: Enumerate Processor MMIO Stale Data bug")

This only causes these perf files to be rebuilt:

  CC       /tmp/build/perf/bench/mem-memcpy-x86-64-asm.o
  CC       /tmp/build/perf/bench/mem-memset-x86-64-asm.o

And addresses this perf build warning:

  Warning: Kernel ABI header at 'tools/arch/x86/include/asm/cpufeatures.h' differs from latest version at 'arch/x86/include/asm/cpufeatures.h'
  diff -u tools/arch/x86/include/asm/cpufeatures.h arch/x86/include/asm/cpufeatures.h

Cc: Adrian Hunter <adrian.hunter at intel.com>
Cc: Alexandre Chartre <alexandre.chartre at oracle.com>
Cc: Andrew Cooper <andrew.cooper3 at citrix.com>
Cc: Borislav Petkov <bp at suse.de>
Cc: Daniel Sneddon <daniel.sneddon at linux.intel.com>
Cc: Dave Hansen <dave.hansen at linux.intel.com>
Cc: Ian Rogers <irogers at google.com>
Cc: Jiri Olsa <jolsa at kernel.org>
Cc: Josh Poimboeuf <jpoimboe at kernel.org>
Cc: Namhyung Kim <namhyung at kernel.org>
Cc: Paolo Bonzini <pbonzini at redhat.com>
Cc: Pawan Gupta <pawan.kumar.gupta at linux.intel.com>
Cc: Peter Zijlstra <peterz at infradead.org>
Cc: Suravee Suthikulpanit <suravee.suthikulpanit at amd.com>
Cc: Wyes Karny <wyes.karny at amd.com>
Link: https://lore.kernel.org/lkml/Yvznmu5oHv0ZDN2w@kernel.org
Signed-off-by: Arnaldo Carvalho de Melo <acme at redhat.com>
(backported from commit 62ed93d1996b3aaeadda59b25ac5b70be59b8a61)
[juergh: Pick only X86_FEATURE_ZEN changes.]
CVE-2024-53114
Signed-off-by: Juerg Haefliger <juerg.haefliger at canonical.com>
---
 tools/arch/x86/include/asm/cpufeatures.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/tools/arch/x86/include/asm/cpufeatures.h b/tools/arch/x86/include/asm/cpufeatures.h
index 861451839cf2..4ea39143ab8a 100644
--- a/tools/arch/x86/include/asm/cpufeatures.h
+++ b/tools/arch/x86/include/asm/cpufeatures.h
@@ -219,7 +219,7 @@
 #define X86_FEATURE_IBRS		( 7*32+25) /* Indirect Branch Restricted Speculation */
 #define X86_FEATURE_IBPB		( 7*32+26) /* Indirect Branch Prediction Barrier */
 #define X86_FEATURE_STIBP		( 7*32+27) /* Single Thread Indirect Branch Predictors */
-#define X86_FEATURE_ZEN			( 7*32+28) /* "" CPU is AMD family 0x17 or above (Zen) */
+#define X86_FEATURE_ZEN			(7*32+28) /* "" CPU based on Zen microarchitecture */
 #define X86_FEATURE_L1TF_PTEINV		( 7*32+29) /* "" L1TF workaround PTE inversion */
 #define X86_FEATURE_IBRS_ENHANCED	( 7*32+30) /* Enhanced IBRS */
 #define X86_FEATURE_MSR_IA32_FEAT_CTL	( 7*32+31) /* "" MSR IA32_FEAT_CTL configured */
-- 
2.48.1