ACK/Cmt: [PATCH 1/1][SRU][Plucky/Oracular] drm/amdgpu: read back register after written for VCN v4.0.5

[Emil Renner Berthing]

Thibault Ferrante wrote:
> Acked-by: Thibault Ferrante <thibault.ferrante at canonical.com>
>
> On 05/06/2025 20:52, You-Sheng Yang wrote:
> > From: "David (Ming Qiang) Wu" <David.Wu3 at amd.com>
> >
> > BugLink: https://bugs.launchpad.net/bugs/2112582
> >
> > On VCN v4.0.5 there is a race condition where the WPTR is not
> > updated after starting from idle when doorbell is used. Adding
> > register read-back after written at function end is to ensure
> > all register writes are done before they can be used.
> >
> > Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/12528
> > Signed-off-by: David (Ming Qiang) Wu <David.Wu3 at amd.com>
> > Reviewed-by: Mario Limonciello <mario.limonciello at amd.com>
> > Tested-by: Mario Limonciello <mario.limonciello at amd.com>
> > Reviewed-by: Alex Deucher <alexander.deucher at amd.com>
> > Reviewed-by: Ruijing Dong <ruijing.dong at amd.com>
> > Signed-off-by: Alex Deucher <alexander.deucher at amd.com>
> > (backported from commit 07c9db090b86e5211188e1b351303fbc673378cf)
>
> There should be a backport note here, it's quite a simple backport for this submission so could be in this spirit:
> [vicamo: adjusted due to missing ecc9ab4e924b drm/amdgpu/vcn4.0.5: split code along instances]

With this fixed, this also looks good to me:

Acked-by: Emil Renner Berthing <emil.renner.berthing at canonical.com>

>
> > Signed-off-by: You-Sheng Yang <vicamo.yang at canonical.com>
> > ---
> >   drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c | 8 ++++++++
> >   1 file changed, 8 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
> > index 4fc307ab0ff83..8166bad4af29e 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
> > @@ -936,6 +936,10 @@ static int vcn_v4_0_5_start_dpg_mode(struct amdgpu_device *adev, int inst_idx, b
> >   			ring->doorbell_index << VCN_RB1_DB_CTRL__OFFSET__SHIFT |
> >   			VCN_RB1_DB_CTRL__EN_MASK);
> >
> > +	/* Keeping one read-back to ensure all register writes are done, otherwise
> > +	 * it may introduce race conditions */
> > +	RREG32_SOC15(VCN, inst_idx, regVCN_RB1_DB_CTRL);
> > +
> >   	return 0;
> >   }
> >
> > @@ -1118,6 +1122,10 @@ static int vcn_v4_0_5_start(struct amdgpu_device *adev)
> >   		tmp |= VCN_RB_ENABLE__RB1_EN_MASK;
> >   		WREG32_SOC15(VCN, i, regVCN_RB_ENABLE, tmp);
> >   		fw_shared->sq.queue_mode &= ~(FW_QUEUE_RING_RESET | FW_QUEUE_DPG_HOLD_OFF);
> > +
> > +		/* Keeping one read-back to ensure all register writes are done, otherwise
> > +		 * it may introduce race conditions */
> > +		RREG32_SOC15(VCN, i, regVCN_RB_ENABLE);
> >   	}
> >
> >   	return 0;
>
>
>
>
>
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