ACK: [SRU] [jammy xilinx-zynqmp 0/3] Update on-chip oscillator clock nodes for Kria

[Hui Wang]

Acked-by: Hui Wang<hui.wang at canonical.com>

On 3/8/24 08:25, Portia Stephens wrote:
> [ Impact ]
>
> * This models on-chip oscillator clock nodes in KV/KR/KD board device trees built for Xilinx products to be in sync with the corresponding board schematic
> * Currently a few clocks were not modelled which are planned to be included now.
> * Most clocks in board device trees are currently included so this should have minimal size impact.
> * The correct and cleanest approach is to model clock sources in Xilinx's application dtsi's in order to reference these clock nodes from the board device tree rather than having duplicated nodes in application overlay dtbo's
>
> [ Test Plan ]
>
> * Normal certification will test that the device tree changes did not introduce a regression on any certified platform.
> * Xilinx will verify they can load the dtbo's for the FPGA during runtime
>
> [ Where problems could occur ]
>
> * There could be an unexpected impact since there are discrepancies between some revA vs revB board device trees, all clock nodes not being modelled to be in sync with board schematics
>
> [ Other Info ]
>
> * BugLink:https://bugs.launchpad.net/bugs/2055241
> * Changes are pulled from Xilinx' 6.6 tree
> https://github.com/Xilinx/linux-xlnx/commit/bd1a7261325afa7526ed12fbaeb8f2e939bd02f8
> https://github.com/Xilinx/linux-xlnx/commit/d9d492b32494611dbcc422d9f365a59df20c69b1
> https://github.com/Xilinx/linux-xlnx/commit/a0fe3083d290f8507922a68daa60cb92d76d56b2
>
> Michal Simek (3):
>    arm64: zynqmp: Sync clock labels with kr260 revB
>    arm64: zynqmp: Describe 25MHz fixed clock for PL GEMs
>    arm64: zynqmp: Fix kr260 clock wiring
>
>   .../boot/dts/xilinx/zynqmp-sck-kd-g-revA.dts  | 12 ++++++++++
>   .../boot/dts/xilinx/zynqmp-sck-kr-g-revA.dts  | 22 ++++++++++++-------
>   .../boot/dts/xilinx/zynqmp-sck-kr-g-revB.dts  |  6 +++++
>   3 files changed, 32 insertions(+), 8 deletions(-)
>
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