[SRU][J][PATCH 0/2] Add PPIN support for Intel EMR cpu

[Roxana Nicolescu]

BugLink: https://bugs.launchpad.net/bugs/2019131

SRU Justification

[Impact]
Intel has introduced support for their new Emerald Rapids CPU.
It was backported to Jammy in #lp2015372 and in #lp2015855.

The remaining feature needed to fully support EMR is PPIN (the Protected
Processor Inventory/Identification Number).
This was recently pushed to upstream in 6.4 in commit
36168bc061b4368ad19e82b06a6463c95d3bb9a7.
The change is very straightforward, it adds a new entry for
EMERALDRAPIDS_X in the cpuids table where cpus that support ppin are
listed. The table is then used in `ppin_init`.

In Jammy, this implementation is missing. Both Amd and Intel have their
own implementation which is doing pretty much the same. Instead of a
list of cpus supported, a switch case is used instead in their init
functions (amd_detect_ppin and intel_ppin_init).
To reduce duplication of code and to help backport smoothly the new
addition of EMR, commit 0dcab41d3487acadf64d0667398e032341bd9918
“x86/cpu: Merge Intel and AMD ppin_init() functions” was backported too.

Thus commits:
- 0dcab41d3487acadf64d0667398e032341bd9918:
"x86/cpu: Merge Intel and AMD ppin_init() functions"
- 36168bc061b4368ad19e82b06a6463c95d3bb9a7:
"x86/cpu: Add Xeon Emerald Rapids to list of CPUs that support PPIN"
are needed to support PPIN for EMR.

[Testing]
Kernel was built on cbd and boot tested on a VM.

[Regression potential]
Very low, it is a small refactor that removes duplication and it
should not affect the functionality.

Tony Luck (2):
  x86/cpu: Merge Intel and AMD ppin_init() functions
  x86/cpu: Add Xeon Emerald Rapids to list of CPUs that support PPIN

 arch/x86/kernel/cpu/amd.c       | 30 -------------
 arch/x86/kernel/cpu/common.c    | 75 +++++++++++++++++++++++++++++++++
 arch/x86/kernel/cpu/mce/intel.c | 42 ------------------
 3 files changed, 75 insertions(+), 72 deletions(-)

-- 
2.34.1