[B][SRU][PATCH 1/2] x86/cpufeatures: Add feature bit RDPRU on AMD

[Po-Hsu Lin]

From: Babu Moger <babu.moger at amd.com>

BugLink: https://bugs.launchpad.net/bugs/1968681

AMD Zen 2 introduces a new RDPRU instruction which is used to give
access to some processor registers that are typically only accessible
when the privilege level is zero.

ECX is used as the implicit register to specify which register to read.
RDPRU places the specified register’s value into EDX:EAX.

For example, the RDPRU instruction can be used to read MPERF and APERF
at CPL > 0.

Add the feature bit so it is visible in /proc/cpuinfo.

Details are available in the AMD64 Architecture Programmer’s Manual:
https://www.amd.com/system/files/TechDocs/24594.pdf

Signed-off-by: Babu Moger <babu.moger at amd.com>
Signed-off-by: Borislav Petkov <bp at suse.de>
Cc: Aaron Lewis <aaronlewis at google.com>
Cc: ak at linux.intel.com
Cc: Fenghua Yu <fenghua.yu at intel.com>
Cc: "H. Peter Anvin" <hpa at zytor.com>
Cc: Ingo Molnar <mingo at redhat.com>
Cc: Josh Poimboeuf <jpoimboe at redhat.com>
Cc: "Peter Zijlstra (Intel)" <peterz at infradead.org>
Cc: robert.hu at linux.intel.com
Cc: Thomas Gleixner <tglx at linutronix.de>
Cc: Thomas Hellstrom <thellstrom at vmware.com>
Cc: x86-ml <x86 at kernel.org>
Link: https://lkml.kernel.org/r/20191007204839.5727.10803.stgit@localhost.localdomain
(backported from commit 9d40b85bb46a99bc95dad3a07787da93b0a018e9)
[PHLin: context adjustment to ignore WBNOINVD change]
Signed-off-by: Po-Hsu Lin <po-hsu.lin at canonical.com>
---
 arch/x86/include/asm/cpufeatures.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h
index 9ff9117..a0d0736 100644
--- a/arch/x86/include/asm/cpufeatures.h
+++ b/arch/x86/include/asm/cpufeatures.h
@@ -288,6 +288,7 @@
 #define X86_FEATURE_CLZERO		(13*32+ 0) /* CLZERO instruction */
 #define X86_FEATURE_IRPERF		(13*32+ 1) /* Instructions Retired Count */
 #define X86_FEATURE_XSAVEERPTR		(13*32+ 2) /* Always save/restore FP error pointers */
+#define X86_FEATURE_RDPRU		(13*32+ 4) /* Read processor register at user level */
 #define X86_FEATURE_AMD_IBPB		(13*32+12) /* "" Indirect Branch Prediction Barrier */
 #define X86_FEATURE_AMD_IBRS		(13*32+14) /* "" Indirect Branch Restricted Speculation */
 #define X86_FEATURE_AMD_STIBP		(13*32+15) /* "" Single Thread Indirect Branch Predictors */
-- 
2.7.4