[J] [PATCH 05/10] drm/i915/display/psr: Handle plane and pipe restrictions at every page flip

[Stefan Bader]

On 02.08.22 04:29, Kai-Heng Feng wrote:
> From: José Roberto de Souza <jose.souza at intel.com>
> 
> BugLink: https://bugs.launchpad.net/bugs/1978252

This ^reference is wrong. I will fix it up to match the other 9 patches but I 
really hope this patch is not there by accident...

-Stefan


> 
> PSR2 selective is not supported over rotated and scaled planes.
> We had the rotation check in intel_psr2_sel_fetch_config_valid()
> but that code path is only execute when a modeset is needed and
> those plane parameters can change without a modeset.
> 
> Pipe selective fetch restrictions are also needed, it could be added
> in intel_psr_compute_config() but pippe scaling is computed after
> it is executed, so leaving as is for now.
> There is no much loss in this approach as it would cause selective
> fetch to not enabled as for alderlake-P and newer will cause it to
> switch to PSR1 that will have the same power-savings as do full pipe
> fetch.
> 
> Also need to check those restricions in the second
> for_each_oldnew_intel_plane_in_state() loop because the state could
> only have a plane that is not affected by those restricitons but
> the damaged area intersect with planes that has those restrictions,
> so a full pipe fetch is required.
> 
> v2:
> - also handling pipe restrictions
> 
> BSpec: 55229
> Reviewed-by: Gwan-gyeong Mun <gwan-gyeong.mun at intel.com> # v1
> Cc: Ville Syrjälä <ville.syrjala at linux.intel.com>
> Cc: Gwan-gyeong Mun <gwan-gyeong.mun at intel.com>
> Signed-off-by: José Roberto de Souza <jose.souza at intel.com>
> Link: https://patchwork.freedesktop.org/patch/msgid/20210930001409.254817-1-jose.souza@intel.com
> (backported from commit ac220f5f754b1d2f4a69428f515c3f1b10d1fad0)
> [khfeng: Textual dependency on refactored codes, and only has functional
> impact when PSR2 selective fetch is enabled.]
> Signed-off-by: Kai-Heng Feng <kai.heng.feng at canonical.com>
> ---
>   drivers/gpu/drm/i915/display/intel_psr.c | 65 +++++++++++++++++-------
>   1 file changed, 46 insertions(+), 19 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
> index 7a0f9f1773553..a314a9ae70401 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -718,11 +718,7 @@ tgl_dc3co_exitline_compute_config(struct intel_dp *intel_dp,
>   static bool intel_psr2_sel_fetch_config_valid(struct intel_dp *intel_dp,
>   					      struct intel_crtc_state *crtc_state)
>   {
> -	struct intel_atomic_state *state = to_intel_atomic_state(crtc_state->uapi.state);
>   	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> -	struct intel_plane_state *plane_state;
> -	struct intel_plane *plane;
> -	int i;
>   
>   	if (!dev_priv->params.enable_psr2_sel_fetch &&
>   	    intel_dp->psr.debug != I915_PSR_DEBUG_ENABLE_SEL_FETCH) {
> @@ -737,14 +733,6 @@ static bool intel_psr2_sel_fetch_config_valid(struct intel_dp *intel_dp,
>   		return false;
>   	}
>   
> -	for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
> -		if (plane_state->uapi.rotation != DRM_MODE_ROTATE_0) {
> -			drm_dbg_kms(&dev_priv->drm,
> -				    "PSR2 sel fetch not enabled, plane rotated\n");
> -			return false;
> -		}
> -	}
> -
>   	/* Wa_14010254185 Wa_14010103792 */
>   	if (IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_C0)) {
>   		drm_dbg_kms(&dev_priv->drm,
> @@ -1547,6 +1535,41 @@ static void intel_psr2_sel_fetch_pipe_alignment(const struct intel_crtc_state *c
>   		drm_warn(&dev_priv->drm, "Missing PSR2 sel fetch alignment with DSC\n");
>   }
>   
> +/*
> + * TODO: Not clear how to handle planes with negative position,
> + * also planes are not updated if they have a negative X
> + * position so for now doing a full update in this cases
> + *
> + * Plane scaling and rotation is not supported by selective fetch and both
> + * properties can change without a modeset, so need to be check at every
> + * atomic commmit.
> + */
> +static bool psr2_sel_fetch_plane_state_supported(const struct intel_plane_state *plane_state)
> +{
> +	if (plane_state->uapi.dst.y1 < 0 ||
> +	    plane_state->uapi.dst.x1 < 0 ||
> +	    plane_state->scaler_id >= 0 ||
> +	    plane_state->uapi.rotation != DRM_MODE_ROTATE_0)
> +		return false;
> +
> +	return true;
> +}
> +
> +/*
> + * Check for pipe properties that is not supported by selective fetch.
> + *
> + * TODO: pipe scaling causes a modeset but skl_update_scaler_crtc() is executed
> + * after intel_psr_compute_config(), so for now keeping PSR2 selective fetch
> + * enabled and going to the full update path.
> + */
> +static bool psr2_sel_fetch_pipe_state_supported(const struct intel_crtc_state *crtc_state)
> +{
> +	if (crtc_state->scaler_state.scaler_id >= 0)
> +		return false;
> +
> +	return true;
> +}
> +
>   int intel_psr2_sel_fetch_update(struct intel_atomic_state *state,
>   				struct intel_crtc *crtc)
>   {
> @@ -1560,6 +1583,11 @@ int intel_psr2_sel_fetch_update(struct intel_atomic_state *state,
>   	if (!crtc_state->enable_psr2_sel_fetch)
>   		return 0;
>   
> +	if (!psr2_sel_fetch_pipe_state_supported(crtc_state)) {
> +		full_update = true;
> +		goto skip_sel_fetch_set_loop;
> +	}
> +
>   	ret = drm_atomic_add_affected_planes(&state->base, &crtc->base);
>   	if (ret)
>   		return ret;
> @@ -1583,13 +1611,7 @@ int intel_psr2_sel_fetch_update(struct intel_atomic_state *state,
>   		    !old_plane_state->uapi.visible)
>   			continue;
>   
> -		/*
> -		 * TODO: Not clear how to handle planes with negative position,
> -		 * also planes are not updated if they have a negative X
> -		 * position so for now doing a full update in this cases
> -		 */
> -		if (new_plane_state->uapi.dst.y1 < 0 ||
> -		    new_plane_state->uapi.dst.x1 < 0) {
> +		if (!psr2_sel_fetch_plane_state_supported(new_plane_state)) {
>   			full_update = true;
>   			break;
>   		}
> @@ -1673,6 +1695,11 @@ int intel_psr2_sel_fetch_update(struct intel_atomic_state *state,
>   		if (!drm_rect_intersect(&inter, &new_plane_state->uapi.dst))
>   			continue;
>   
> +		if (!psr2_sel_fetch_plane_state_supported(new_plane_state)) {
> +			full_update = true;
> +			break;
> +		}
> +
>   		sel_fetch_area = &new_plane_state->psr2_sel_fetch_area;
>   		sel_fetch_area->y1 = inter.y1 - new_plane_state->uapi.dst.y1;
>   		sel_fetch_area->y2 = inter.y2 - new_plane_state->uapi.dst.y1;

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