[PATCH 01/16][SRU][OEM-5.14/Jammy] x86/cpufeatures: Add AMD Collaborative Processor Performance Control feature flag

[You-Sheng Yang]

From: Huang Rui <ray.huang at amd.com>

BugLink: https://bugs.launchpad.net/bugs/1956509

Add Collaborative Processor Performance Control feature flag for AMD
processors.

This feature flag will be used on the following AMD P-State driver. The
AMD P-State driver has two approaches to implement the frequency control
behavior. That depends on the CPU hardware implementation. One is "Full
MSR Support" and another is "Shared Memory Support". The feature flag
indicates the current processors with "Full MSR Support".

Acked-by: Borislav Petkov <bp at suse.de>
Signed-off-by: Huang Rui <ray.huang at amd.com>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki at intel.com>
(cherry picked from commit d341db8f48ea43314f489921962c7f8f4ec27239)
Signed-off-by: You-Sheng Yang <vicamo.yang at canonical.com>
---
 arch/x86/include/asm/cpufeatures.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h
index 4423759f619c..b7aebfccdfab 100644
--- a/arch/x86/include/asm/cpufeatures.h
+++ b/arch/x86/include/asm/cpufeatures.h
@@ -313,6 +313,7 @@
 #define X86_FEATURE_AMD_SSBD		(13*32+24) /* "" Speculative Store Bypass Disable */
 #define X86_FEATURE_VIRT_SSBD		(13*32+25) /* Virtualized Speculative Store Bypass Disable */
 #define X86_FEATURE_AMD_SSB_NO		(13*32+26) /* "" Speculative Store Bypass is fixed in hardware. */
+#define X86_FEATURE_CPPC		(13*32+27) /* Collaborative Processor Performance Control */
 
 /* Thermal and Power Management Leaf, CPUID level 0x00000006 (EAX), word 14 */
 #define X86_FEATURE_DTHERM		(14*32+ 0) /* Digital Thermal Sensor */
-- 
2.34.1