ACK: [SRU] [H/I/OEM-5.10/OEM-5.13/OEM-5.14] [PATCH 0/4] Let NVMe with HMB use native power control again

[Tim Gardner]

Acked-by: Tim Gardner <tim.gardner at canonical.com>

On 11/6/21 6:10 AM, Kai-Heng Feng wrote:
> BugLink: https://bugs.launchpad.net/bugs/1950042
> 
> [Impact]
> NVMe with HMB may still do DMA during suspend, so there was a commit
> that put the NVMe to PCI D3 during suspend to prevent DMA activities.
> However, this makes them consumes much more power because modern NVMe
> requires to stay at PCI D0 to make its natve power control work.
> 
> [Fix]
> Instead of put the NVMe to PCI D3 and reset it afterward, simply disable
> HMB and re-enable HMB, for suspend and resume respectively.
> 
> [Test]
> On affected system, Intel SoC can only reach PC3 during suspend.
> With the SRU applied, the Intel SoC can reach PC10 and SLP_S0 and use
> significant less power.
> 
> [Where problems could occur]
> The original approach, i.e. disable NVMe and put it to PCI D3 to prevent
> DMA activies, was just a precaution. There wasn't any case that
> indicates it happens in practice.
> 
> This is a different approach to the same problem, which is a theoretical
> problem.
> 
> Keith Busch (4):
>    nvme-pci: use attribute group for cmb sysfs
>    nvme-pci: cmb sysfs: one file, one value
>    nvme-pci: disable hmb on idle suspend
>    nvme: allow user toggling hmb usage
> 
>   drivers/nvme/host/pci.c | 165 +++++++++++++++++++++++++++++++---------
>   1 file changed, 131 insertions(+), 34 deletions(-)
> 

-- 
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Tim Gardner
Canonical, Inc