APPLIED (hirsute/5.11): [PATCH 1/2][SRU][HIRSUTE][RISCV] Revert "SiFive Unleashed CPUFreq"

[Andrea Righi]

Applied only PATCH 1/2 to hirsute/5.11, because PATCH 2/2 doesn't apply.

Thanks,
-Andrea

On Tue, Mar 02, 2021 at 11:22:57AM +0000, Colin King wrote:
> From: Colin Ian King <colin.king at canonical.com>
> 
> The SiFive Unleashed CPU frequency is known to be unreliabe especially
> when using the latest device tree and the default Ubuntu CPU frequency
> schedule settings. Revert the CPU Frequency commit for now until we
> get a suitable upstream fix that works more reliably with our default
> Ubuntu configs.
> 
> BugLink: https://bugs.launchpad.net/bugs/1917433
> 
> This reverts commit 3949df6ecdca04339bc8a3925c2ba7f881cf82b1.
> ---
>  arch/riscv/Kconfig                            |  8 -----
>  arch/riscv/boot/dts/sifive/fu540-c000.dtsi    |  5 ---
>  .../boot/dts/sifive/hifive-unleashed-a00.dts  | 34 -------------------
>  arch/riscv/configs/defconfig                  |  5 ---
>  4 files changed, 52 deletions(-)
> 
> diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
> index b0a7a37b2ae1..3230c1d48562 100644
> --- a/arch/riscv/Kconfig
> +++ b/arch/riscv/Kconfig
> @@ -396,14 +396,6 @@ config BUILTIN_DTB
>  	depends on RISCV_M_MODE
>  	depends on OF
>  
> -menu "CPU Power Management"
> -
> -source "drivers/cpuidle/Kconfig"
> -
> -source "drivers/cpufreq/Kconfig"
> -
> -endmenu
> -
>  menu "Power management options"
>  
>  source "kernel/power/Kconfig"
> diff --git a/arch/riscv/boot/dts/sifive/fu540-c000.dtsi b/arch/riscv/boot/dts/sifive/fu540-c000.dtsi
> index 023a8fd14cf6..7db861053483 100644
> --- a/arch/riscv/boot/dts/sifive/fu540-c000.dtsi
> +++ b/arch/riscv/boot/dts/sifive/fu540-c000.dtsi
> @@ -30,7 +30,6 @@ cpu0: cpu at 0 {
>  			i-cache-size = <16384>;
>  			reg = <0>;
>  			riscv,isa = "rv64imac";
> -			clocks = <&prci PRCI_CLK_COREPLL>;
>  			status = "disabled";
>  			cpu0_intc: interrupt-controller {
>  				#interrupt-cells = <1>;
> @@ -55,7 +54,6 @@ cpu1: cpu at 1 {
>  			reg = <1>;
>  			riscv,isa = "rv64imafdc";
>  			tlb-split;
> -			clocks = <&prci PRCI_CLK_COREPLL>;
>  			next-level-cache = <&l2cache>;
>  			cpu1_intc: interrupt-controller {
>  				#interrupt-cells = <1>;
> @@ -80,7 +78,6 @@ cpu2: cpu at 2 {
>  			reg = <2>;
>  			riscv,isa = "rv64imafdc";
>  			tlb-split;
> -			clocks = <&prci PRCI_CLK_COREPLL>;
>  			next-level-cache = <&l2cache>;
>  			cpu2_intc: interrupt-controller {
>  				#interrupt-cells = <1>;
> @@ -105,7 +102,6 @@ cpu3: cpu at 3 {
>  			reg = <3>;
>  			riscv,isa = "rv64imafdc";
>  			tlb-split;
> -			clocks = <&prci PRCI_CLK_COREPLL>;
>  			next-level-cache = <&l2cache>;
>  			cpu3_intc: interrupt-controller {
>  				#interrupt-cells = <1>;
> @@ -130,7 +126,6 @@ cpu4: cpu at 4 {
>  			reg = <4>;
>  			riscv,isa = "rv64imafdc";
>  			tlb-split;
> -			clocks = <&prci PRCI_CLK_COREPLL>;
>  			next-level-cache = <&l2cache>;
>  			cpu4_intc: interrupt-controller {
>  				#interrupt-cells = <1>;
> diff --git a/arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts b/arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts
> index c8a47bf32f04..9bafe4673cca 100644
> --- a/arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts
> +++ b/arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts
> @@ -78,40 +78,6 @@ gpio-restart {
>  		compatible = "gpio-restart";
>  		gpios = <&gpio 10 GPIO_ACTIVE_LOW>;
>  	};
> -
> -	fu540_c000_opp_table: opp-table {
> -		compatible = "operating-points-v2";
> -		opp-shared;
> -
> -		opp-350000000 {
> -			opp-hz = /bits/ 64 <350000000>;
> -		};
> -		opp-700000000 {
> -			opp-hz = /bits/ 64 <700000000>;
> -		};
> -		opp-999999999 {
> -			opp-hz = /bits/ 64 <999999999>;
> -		};
> -		opp-1400000000 {
> -			opp-hz = /bits/ 64 <1400000000>;
> -		};
> -	};
> -};
> -
> -&cpu0 {
> -	operating-points-v2 = <&fu540_c000_opp_table>;
> -};
> -&cpu1 {
> -	operating-points-v2 = <&fu540_c000_opp_table>;
> -};
> -&cpu2 {
> -	operating-points-v2 = <&fu540_c000_opp_table>;
> -};
> -&cpu3 {
> -	operating-points-v2 = <&fu540_c000_opp_table>;
> -};
> -&cpu4 {
> -	operating-points-v2 = <&fu540_c000_opp_table>;
>  };
>  
>  &uart0 {
> diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig
> index 58f4bce82d91..4da4886246a4 100644
> --- a/arch/riscv/configs/defconfig
> +++ b/arch/riscv/configs/defconfig
> @@ -17,11 +17,6 @@ CONFIG_BPF_SYSCALL=y
>  CONFIG_SOC_SIFIVE=y
>  CONFIG_SOC_VIRT=y
>  CONFIG_SMP=y
> -CONFIG_CPU_IDLE=y
> -CONFIG_CPU_FREQ=y
> -CONFIG_CPU_FREQ_STAT=y
> -CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE=y
> -CONFIG_CPUFREQ_DT=y
>  CONFIG_MODULES=y
>  CONFIG_MODULE_UNLOAD=y
>  CONFIG_NET=y
> -- 
> 2.29.2
> 
> 
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