[PATCH 3/3][SRU][U/OEM-5.13] perf/x86/intel: Fix instructions:ppp support in Sapphire Rapids

You-Sheng Yang vicamo.yang at canonical.com
Tue Jul 13 04:36:55 UTC 2021

From: Kan Liang <kan.liang at linux.intel.com>

BugLink: https://bugs.launchpad.net/bugs/1933617

Perf errors out when sampling instructions:ppp.

$ perf record -e instructions:ppp -- true
The sys_perf_event_open() syscall returned with 22 (Invalid argument)
for event (instructions:ppp).

The instruction PDIR is only available on the fixed counter 0. The event
constraint has been updated to fixed0_constraint in
icl_get_event_constraints(). The Sapphire Rapids codes unconditionally
error out for the event which is not available on the GP counter 0.

Make the instructions:ppp an exception.

Fixes: 61b985e3e775 ("perf/x86/intel: Add perf core PMU support for Sapphire Rapids")
Reported-by: Yasin, Ahmad <ahmad.yasin at intel.com>
Signed-off-by: Kan Liang <kan.liang at linux.intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz at infradead.org>
Cc: stable at vger.kernel.org
Link: https://lore.kernel.org/r/1624029174-122219-4-git-send-email-kan.liang@linux.intel.com
(cherry picked from commit 1d5c7880992a06679585e7e568cc679c0c5fd4f2)
Signed-off-by: You-Sheng Yang <vicamo.yang at canonical.com>
 arch/x86/events/intel/core.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c
index 93b6198af4c1..d76be3bba11e 100644
--- a/arch/x86/events/intel/core.c
+++ b/arch/x86/events/intel/core.c
@@ -4032,8 +4032,10 @@ spr_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
 	 * The :ppp indicates the Precise Distribution (PDist) facility, which
 	 * is only supported on the GP counter 0. If a :ppp event which is not
 	 * available on the GP counter 0, error out.
+	 * Exception: Instruction PDIR is only available on the fixed counter 0.
-	if (event->attr.precise_ip == 3) {
+	if ((event->attr.precise_ip == 3) &&
+	    !constraint_match(&fixed0_constraint, event->hw.config)) {
 		if (c->idxmsk64 & BIT_ULL(0))
 			return &counter0_constraint;

More information about the kernel-team mailing list