[PATCH 0/3][SRU][U/OEM-5.13] Fix broken PMU hardware on ADL
vicamo.yang at canonical.com
Tue Jul 13 04:36:52 UTC 2021
PMU hardware init failed on ADL big-only configurations.
Fixes in 5.14-rc1 required to address this issue.
While these fixes are only needed on ADL big-only configurations and
stepping >= 0x03 (those less than 0x03 are engineering samples and
ignored here), one must make sure an appropriate hw is used for
validation. The dmesg should contain:
NMI watchdog: Enabled. Permanently consumes one hw-PMU counter
[Where problems could occur]
This, along with the code segments to be fixed, belongs to a new hardware
platform, and are splited by switch-cases.
Kan Liang (3):
perf/x86/intel: Fix fixed counter check warning for some Alder Lake
perf/x86/intel: Add more events requires FRONTEND MSR on Sapphire
perf/x86/intel: Fix instructions:ppp support in Sapphire Rapids
arch/x86/events/intel/core.c | 15 ++++++++++++---
1 file changed, 12 insertions(+), 3 deletions(-)
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