[SRU][F][PULL][PATCH v2 11/23] Revert "UBUNTU: SAUCE: mlxbf-gige: remove gpio interrupt coalesce resources"

[Asmaa Mnebhi]

BugLink: https://bugs.launchpad.net/bugs/1934923

This reverts commit d11fc64e9e4bd09536448b4571660e1ad38a6a83.

Signed-off-by: Asmaa Mnebhi <asmaa at nvidia.com>
---
 .../ethernet/mellanox/mlxbf_gige/mlxbf_gige.h |  4 +++
 .../mellanox/mlxbf_gige/mlxbf_gige_main.c     |  2 +-
 .../mellanox/mlxbf_gige/mlxbf_gige_mdio.c     | 34 +++++++++++++++++++
 3 files changed, 39 insertions(+), 1 deletion(-)

diff --git a/drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige.h b/drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige.h
index 27786512d35f..63e07e60108d 100644
--- a/drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige.h
+++ b/drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige.h
@@ -75,6 +75,8 @@ struct mlxbf_gige {
 	void __iomem *mdio_io;
 	struct mii_bus *mdiobus;
 	void __iomem *gpio_io;
+	void __iomem *cause_rsh_coalesce0_io;
+	void __iomem *cause_gpio_arm_coalesce0_io;
 	u32 phy_int_gpio_mask;
 	spinlock_t lock;
 	spinlock_t gpio_lock;
@@ -141,6 +143,8 @@ enum mlxbf_gige_res {
 	MLXBF_GIGE_RES_MAC,
 	MLXBF_GIGE_RES_MDIO9,
 	MLXBF_GIGE_RES_GPIO0,
+	MLXBF_GIGE_RES_CAUSE_RSH_COALESCE0,
+	MLXBF_GIGE_RES_CAUSE_GPIO_ARM_COALESCE0,
 	MLXBF_GIGE_RES_LLU,
 	MLXBF_GIGE_RES_PLU
 };
diff --git a/drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige_main.c b/drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige_main.c
index 0a0e5ea76e66..a4ac1dc947d0 100644
--- a/drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige_main.c
+++ b/drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige_main.c
@@ -19,7 +19,7 @@
 #include "mlxbf_gige_regs.h"
 
 #define DRV_NAME    "mlxbf_gige"
-#define DRV_VERSION "1.6"
+#define DRV_VERSION "1.5"
 
 static void mlxbf_gige_set_mac_rx_filter(struct mlxbf_gige *priv,
 					 unsigned int index, u64 dmac)
diff --git a/drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige_mdio.c b/drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige_mdio.c
index 13e9af57fc77..464bfac9a650 100644
--- a/drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige_mdio.c
+++ b/drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige_mdio.c
@@ -71,6 +71,16 @@
 				 FIELD_PREP(MLXBF_GIGE_MDIO_CFG_MDIO_IN_SAMP_MASK, 6) | \
 				 FIELD_PREP(MLXBF_GIGE_MDIO_CFG_MDIO_OUT_SAMP_MASK, 13))
 
+/* The PHY interrupt line is shared with other interrupt lines such
+ * as GPIO and SMBus. So use YU registers to determine whether the
+ * interrupt comes from the PHY.
+ */
+#define MLXBF_GIGE_CAUSE_RSH_COALESCE0_GPIO_CAUSE_MASK	0x10
+#define MLXBF_GIGE_GPIO_CAUSE_IRQ_IS_SET(val) \
+	((val) & MLXBF_GIGE_CAUSE_RSH_COALESCE0_GPIO_CAUSE_MASK)
+
+#define MLXBF_GIGE_GPIO_BLOCK0_MASK	BIT(0)
+
 #define MLXBF_GIGE_GPIO_CAUSE_FALL_EN		0x48
 #define MLXBF_GIGE_GPIO_CAUSE_OR_CAUSE_EVTEN0	0x80
 #define MLXBF_GIGE_GPIO_CAUSE_OR_EVTEN0		0x94
@@ -211,6 +221,10 @@ irqreturn_t mlxbf_gige_mdio_handle_phy_interrupt(int irq, void *dev_id)
 
 	/* Clear interrupt when done, otherwise, no further interrupt
 	 * will be triggered.
+	 * Writing 0x1 to the clear cause register also clears the
+	 * following registers:
+	 * cause_gpio_arm_coalesce0
+	 * cause_rsh_coalesce0
 	 */
 	val = readl(priv->gpio_io +
 			MLXBF_GIGE_GPIO_CAUSE_OR_CLRCAUSE);
@@ -247,6 +261,26 @@ int mlxbf_gige_mdio_probe(struct platform_device *pdev, struct mlxbf_gige *priv)
 	if (!priv->gpio_io)
 		return -ENOMEM;
 
+	res = platform_get_resource(pdev, IORESOURCE_MEM,
+				    MLXBF_GIGE_RES_CAUSE_RSH_COALESCE0);
+	if (!res)
+		return -ENODEV;
+
+	priv->cause_rsh_coalesce0_io =
+		devm_ioremap(dev, res->start, resource_size(res));
+	if (!priv->cause_rsh_coalesce0_io)
+		return -ENOMEM;
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM,
+				    MLXBF_GIGE_RES_CAUSE_GPIO_ARM_COALESCE0);
+	if (!res)
+		return -ENODEV;
+
+	priv->cause_gpio_arm_coalesce0_io =
+		devm_ioremap(dev, res->start, resource_size(res));
+	if (!priv->cause_gpio_arm_coalesce0_io)
+		return -ENOMEM;
+
 	/* Configure mdio parameters */
 	writel(MLXBF_GIGE_MDIO_CFG_VAL,
 	       priv->mdio_io + MLXBF_GIGE_MDIO_CFG_OFFSET);
-- 
2.30.1