ACK: [PATCH 0/2][F/G/U/OEM-5.10] UBUNTU: SAUCE: Fix the video can't output through WD19TB connected on TGL's Type-C port during cold-boot

[Kleber Souza]

On 27.01.21 07:10, Koba Ko wrote:
> BugLink: https://bugs.launchpad.net/bugs/1913372
> 
> [Impact]
> WD19TB would report the number of lane(2-lane) and it works well on Type-C port
> of TGL platform. Change the LTTPR mode to non-transparent mode, WD19TB would
> report the larger number of lane(4-lane). It's over the type-c port's bandwidth.
> 
> [Fix]
> The patch is provided by Imre(https://patchwork.freedesktop.org/series/86267/).
> Calculate the PBN divider value based on the rate and lane count link parameters
> that the driver uses for all other computation.
> 
> [Test Case]
> 1. Connected the WD19TB with the TGL platform's Type-C port and
> connected the external monitor on WD19TB with HDMI/Displayport.
> 2. Cold boot the TGL platform.
> 3. Check the monitor can be blinked and the video can output to the monitor.
> 
> [Where problems could occur]
> It's correct to calculate the PBN divider based on the source's rate
> and lane count, not the mst's capability.
> 
> Imre Deak (2):
>    drm/dp/mst: Export drm_dp_get_vc_payload_bw()
>    drm/i915: Fix the MST PBN divider calculation
> 
>   drivers/gpu/drm/drm_dp_mst_topology.c       | 24 +++++++++++++++------
>   drivers/gpu/drm/i915/display/intel_dp_mst.c |  4 +++-
>   include/drm/drm_dp_mst_helper.h             |  1 +
>   3 files changed, 22 insertions(+), 7 deletions(-)
> 

With Stefan's comments addressed:

Acked-by: Kleber Sacilotto de Souza <kleber.souza at canonical.com>