[SRU][Focal][PATCH 1/1] ice: Fix bad register reads

[Michael Reed]

From: Anirudh Venkataramanan <anirudh.venkataramanan at intel.com>

The "ethtool -d" handler reads registers in the ice_regs_dump_list array
and returns read values back to the userspace.

The register offsets PFINT0_ITR* are not valid as per the specification
and reading these causes a "unable to handle kernel paging request" bug
in the driver. Remove these registers from ice_regs_dump_list.

BugLink:  https://launchpad.net/bugs/1939855
Signed-off-by: Anirudh Venkataramanan <anirudh.venkataramanan at intel.com>
Signed-off-by: Tony Nguyen <anthony.l.nguyen at intel.com>
Tested-by: Andrew Bowers <andrewx.bowers at intel.com>
Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher at intel.com>
(cherry picked from commit 1fba4a8a92706c89716449b1aab1b6879f438d34)
Signed-off-by: Michael Reed <Michael.Reed at canonical.com>
---
 drivers/net/ethernet/intel/ice/ice_ethtool.c    | 3 ---
 drivers/net/ethernet/intel/ice/ice_hw_autogen.h | 3 ---
 2 files changed, 6 deletions(-)

diff --git a/drivers/net/ethernet/intel/ice/ice_ethtool.c b/drivers/net/ethernet/intel/ice/ice_ethtool.c
index fc9ff985a62b..8e38ecd9179b 100644
--- a/drivers/net/ethernet/intel/ice/ice_ethtool.c
+++ b/drivers/net/ethernet/intel/ice/ice_ethtool.c
@@ -138,9 +138,6 @@ static const u32 ice_regs_dump_list[] = {
 	QINT_RQCTL(0),
 	PFINT_OICR_ENA,
 	QRX_ITR(0),
-	PF0INT_ITR_0(0),
-	PF0INT_ITR_1(0),
-	PF0INT_ITR_2(0),
 };
 
 struct ice_priv_flag {
diff --git a/drivers/net/ethernet/intel/ice/ice_hw_autogen.h b/drivers/net/ethernet/intel/ice/ice_hw_autogen.h
index f2bb83af4d9e..c20718f9d5a6 100644
--- a/drivers/net/ethernet/intel/ice/ice_hw_autogen.h
+++ b/drivers/net/ethernet/intel/ice/ice_hw_autogen.h
@@ -6,9 +6,6 @@
 #ifndef _ICE_HW_AUTOGEN_H_
 #define _ICE_HW_AUTOGEN_H_
 
-#define PF0INT_ITR_0(_i)			(0x03000004 + ((_i) * 4096))
-#define PF0INT_ITR_1(_i)			(0x03000008 + ((_i) * 4096))
-#define PF0INT_ITR_2(_i)			(0x0300000C + ((_i) * 4096))
 #define QTX_COMM_DBELL(_DBQM)			(0x002C0000 + ((_DBQM) * 4))
 #define QTX_COMM_HEAD(_DBQM)			(0x000E0000 + ((_DBQM) * 4))
 #define QTX_COMM_HEAD_HEAD_S			0
-- 
2.25.1