NACK: [PATCH 1/1 V2][SRU][Unstable] drm/i915/gen9bc: Handle TGP PCH during suspend/resume
Koba Ko
koba.ko at canonical.com
Wed Apr 7 02:19:54 UTC 2021
On Tue, Apr 6, 2021 at 11:19 PM Seth Forshee <seth.forshee at canonical.com> wrote:
>
> On Tue, Apr 06, 2021 at 03:06:25PM +0800, Koba Ko wrote:
> > From: Tejas Upadhyay <tejaskumarx.surendrakumar.upadhyay at intel.com>
> >
> > BugLink: https://bugs.launchpad.net/bugs/1913682
> >
> > For Legacy S3 suspend/resume GEN9 BC needs to enable and
> > setup TGP PCH.
> >
> > v2:
> > * Move Wa_14010685332 into it's own function - vsyrjala
> > * Add TODO comment about figuring out if we can move this workaround - imre
> > v3:
> > * Rename cnp_irq_post_reset() to cnp_display_clock_wa()
> > * Add TODO item mentioning we need to clarify which platforms this
> > workaround applies to
> > * Just use ibx_irq_reset() in gen8_irq_reset(). This code should be
> > functionally equivalent on gen9 bc to the code v2 added
> > * Drop icp_hpd_irq_setup() call in spt_hpd_irq_setup(), this looks to be
> > more or less identical to spt_hpd_irq_setup() minus additionally enabling
> > one port. Will update i915 to use icp_hpd_irq_setup() for ICP in a
> > separate patch.
> > v4:
> > * Revert Wa_14010685332 system list in comments to how it was before
> > * Add back HAS_PCH_SPLIT() check before calling ibx_irq_reset()
> >
> > Cc: Matt Roper <matthew.d.roper at intel.com>
> > Signed-off-by: Tejas Upadhyay <tejaskumarx.surendrakumar.upadhyay at intel.com>
> > Signed-off-by: Lyude Paul <lyude at redhat.com>
> > Reviewed-by: Imre Deak <imre.deak at intel.com>
> > Link: https://patchwork.freedesktop.org/patch/msgid/20210217180016.1937401-1-lyude@redhat.com
> > (cherry picked from commit 59b7cb44cffde6ab5b8ace1aef9b79f50be1c3eb
> > drmtip)
>
> Can you put the full URI for the git repo? We accept linux-next because
> that is well-known, I don't think drmtip is widely known enough to
> deserve the same treatment.
ok, will append the git repo.
>
> > Signed-off-by: Koba Ko <koba.ko at canonical.com>
> >
> > V2: Resolve the conflict for unstable kernel.
>
> Above you say it's a cherry pick, but here you say you resolved
> conflicts. Can you clarify? If there were conflicts then it is a
> backport, not a cherry pick.
> Thanks,
> Seth
>
> > ---
> > drivers/gpu/drm/i915/i915_irq.c | 49 +++++++++++++++++++++------------
> > 1 file changed, 32 insertions(+), 17 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> > index 1a701367a718..d0f317de9067 100644
> > --- a/drivers/gpu/drm/i915/i915_irq.c
> > +++ b/drivers/gpu/drm/i915/i915_irq.c
> > @@ -3023,6 +3023,24 @@ static void valleyview_irq_reset(struct drm_i915_private *dev_priv)
> > spin_unlock_irq(&dev_priv->irq_lock);
> > }
> >
> > +static void cnp_display_clock_wa(struct drm_i915_private *dev_priv)
> > +{
> > + struct intel_uncore *uncore = &dev_priv->uncore;
> > +
> > + /*
> > + * Wa_14010685332:cnp/cmp,tgp,adp
> > + * TODO: Clarify which platforms this applies to
> > + * TODO: Figure out if this workaround can be applied in the s0ix suspend/resume handlers as
> > + * on earlier platforms and whether the workaround is also needed for runtime suspend/resume
> > + */
> > + if (INTEL_PCH_TYPE(dev_priv) == PCH_CNP ||
> > + (INTEL_PCH_TYPE(dev_priv) >= PCH_TGP && INTEL_PCH_TYPE(dev_priv) < PCH_DG1)) {
> > + intel_uncore_rmw(uncore, SOUTH_CHICKEN1, SBCLK_RUN_REFCLK_DIS,
> > + SBCLK_RUN_REFCLK_DIS);
> > + intel_uncore_rmw(uncore, SOUTH_CHICKEN1, SBCLK_RUN_REFCLK_DIS, 0);
> > + }
> > +}
> > +
> > static void gen8_irq_reset(struct drm_i915_private *dev_priv)
> > {
> > struct intel_uncore *uncore = &dev_priv->uncore;
> > @@ -3046,6 +3064,8 @@ static void gen8_irq_reset(struct drm_i915_private *dev_priv)
> >
> > if (HAS_PCH_SPLIT(dev_priv))
> > ibx_irq_reset(dev_priv);
> > +
> > + cnp_display_clock_wa(dev_priv);
> > }
> >
> > static void gen11_display_irq_reset(struct drm_i915_private *dev_priv)
> > @@ -3087,15 +3107,7 @@ static void gen11_display_irq_reset(struct drm_i915_private *dev_priv)
> > if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
> > GEN3_IRQ_RESET(uncore, SDE);
> >
> > - /* Wa_14010685332:cnp/cmp,tgp,adp */
> > - if (INTEL_PCH_TYPE(dev_priv) == PCH_CNP ||
> > - (INTEL_PCH_TYPE(dev_priv) >= PCH_TGP &&
> > - INTEL_PCH_TYPE(dev_priv) < PCH_DG1)) {
> > - intel_uncore_rmw(uncore, SOUTH_CHICKEN1,
> > - SBCLK_RUN_REFCLK_DIS, SBCLK_RUN_REFCLK_DIS);
> > - intel_uncore_rmw(uncore, SOUTH_CHICKEN1,
> > - SBCLK_RUN_REFCLK_DIS, 0);
> > - }
> > + cnp_display_clock_wa(dev_priv);
> > }
> >
> > static void gen11_irq_reset(struct drm_i915_private *dev_priv)
> > @@ -3747,9 +3759,19 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
> > }
> > }
> >
> > +static void icp_irq_postinstall(struct drm_i915_private *dev_priv)
> > +{
> > + struct intel_uncore *uncore = &dev_priv->uncore;
> > + u32 mask = SDE_GMBUS_ICP;
> > +
> > + GEN3_IRQ_INIT(uncore, SDE, ~mask, 0xffffffff);
> > +}
> > +
> > static void gen8_irq_postinstall(struct drm_i915_private *dev_priv)
> > {
> > - if (HAS_PCH_SPLIT(dev_priv))
> > + if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
> > + icp_irq_postinstall(dev_priv);
> > + else if (HAS_PCH_SPLIT(dev_priv))
> > ibx_irq_postinstall(dev_priv);
> >
> > gen8_gt_irq_postinstall(&dev_priv->gt);
> > @@ -3758,13 +3780,6 @@ static void gen8_irq_postinstall(struct drm_i915_private *dev_priv)
> > gen8_master_intr_enable(dev_priv->uncore.regs);
> > }
> >
> > -static void icp_irq_postinstall(struct drm_i915_private *dev_priv)
> > -{
> > - struct intel_uncore *uncore = &dev_priv->uncore;
> > - u32 mask = SDE_GMBUS_ICP;
> > -
> > - GEN3_IRQ_INIT(uncore, SDE, ~mask, 0xffffffff);
> > -}
> >
> > static void gen11_irq_postinstall(struct drm_i915_private *dev_priv)
> > {
> > --
> > 2.25.1
> >
> >
> > --
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