[PATCHv2 0/8][Hirsute][generic & riscv] Fixup old unmatched patches, thus fix l2 cache
Dimitri John Ledkov
xnox at ubuntu.com
Thu Apr 1 11:54:49 UTC 2021
Revert old unmatched patches.
Cherrypick newer versions of the same patches from unstable / v5.12.
This update the sifive l2 cache driver, which fixes failure to
cold-boot. Tested on unmatched board cold boot & sort-reset
successfully.
This is targetting src:linux & src:linux-riscv for Hirsute GA.
BugLink: https://bugs.launchpad.net/bugs/1920916
Due to reverts and for clarity, the net diff of this pull request is
attached below, generated with git request-pull -p:
The following changes since commit b576dd670abcb68538f34570c6063f8a65194bd0:
UBUNTU: Ubuntu-riscv-5.11.0-1004.4 (2021-03-19 18:21:28 +0100)
are available in the Git repository at:
https://git.launchpad.net/~xnox/ubuntu/+source/linux-riscv/+git/hirsute fixup-old-patches-v2
for you to fetch changes up to 57611b60f9bbb873c30727c1822f17f8a2b5045a:
dt-bindings: gpio: Update DT binding docs to support SiFive FU740 SoC (2021-04-01 11:17:29 +0100)
----------------------------------------------------------------
Dimitri John Ledkov (3):
Revert "RISC-V: sifive_l2_cache: Update L2 cache driver to support SiFive FU740"
Revert "RISC-V: Update l2 cache DT documentation to add support for SiFive FU740"
Revert "dt-bindings: riscv: Update DT binding docs to support SiFive FU740 SoC"
Yash Shah (5):
dt-bindings: riscv: Update l2 cache DT documentation to add support for SiFive FU740
RISC-V: sifive_l2_cache: Update L2 cache driver to support SiFive FU740
dt-bindings: riscv: Update DT binding docs to support SiFive FU740 SoC
dt-bindings: pwm: Update DT binding docs to support SiFive FU740 SoC
dt-bindings: gpio: Update DT binding docs to support SiFive FU740 SoC
.../devicetree/bindings/gpio/sifive,gpio.yaml | 6 ++---
.../devicetree/bindings/i2c/i2c-ocores.txt | 10 ++++----
.../devicetree/bindings/riscv/sifive-l2-cache.yaml | 7 ++----
drivers/soc/sifive/sifive_l2_cache.c | 28 +++++-----------------
4 files changed, 16 insertions(+), 35 deletions(-)
diff --git a/Documentation/devicetree/bindings/gpio/sifive,gpio.yaml b/Documentation/devicetree/bindings/gpio/sifive,gpio.yaml
index b71d261ea504..ab22056f8b44 100644
--- a/Documentation/devicetree/bindings/gpio/sifive,gpio.yaml
+++ b/Documentation/devicetree/bindings/gpio/sifive,gpio.yaml
@@ -13,9 +13,9 @@ maintainers:
properties:
compatible:
items:
- - enum:
- - sifive,fu540-c000-gpio
- - sifive,fu740-c000-gpio
+ - enum:
+ - sifive,fu540-c000-gpio
+ - sifive,fu740-c000-gpio
- const: sifive,gpio0
reg:
diff --git a/Documentation/devicetree/bindings/i2c/i2c-ocores.txt b/Documentation/devicetree/bindings/i2c/i2c-ocores.txt
index efd0f8537128..a37c9455b244 100644
--- a/Documentation/devicetree/bindings/i2c/i2c-ocores.txt
+++ b/Documentation/devicetree/bindings/i2c/i2c-ocores.txt
@@ -3,14 +3,14 @@ Device tree configuration for i2c-ocores
Required properties:
- compatible : "opencores,i2c-ocores"
"aeroflexgaisler,i2cmst"
- "sifive,<chip>-i2c", "sifive,i2c0"
+ "sifive,fu540-c000-i2c", "sifive,i2c0"
For Opencore based I2C IP block reimplemented in
+ FU540-C000 SoC.
"sifive,fu740-c000-i2c", "sifive,i2c0"
For Opencore based I2C IP block reimplemented in
- SiFive SoC. Supported compatible strings are:
- "sifive,fu540-c000-i2c" and "sifive,fu740-c000-i2c"
- Please refer to sifive-blocks-ip-versioning.txt
- for additional details.
+ FU740-C000 SoC.
+ Please refer to sifive-blocks-ip-versioning.txt for
+ additional details.
- reg : bus address start and address range size of device
- clocks : handle to the controller clock; see the note below.
Mutually exclusive with opencores,ip-clock-frequency
diff --git a/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml b/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml
index 749265c0aaba..6a576dce1f31 100644
--- a/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml
+++ b/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml
@@ -55,16 +55,13 @@ properties:
cache-unified: true
interrupts:
- description: |
- Must contain 3 entries for FU540 (DirError, DataError and DataFail) or 4
- entries for other chips (DirError, DirFail, DataError, DataFail signals)
minItems: 3
maxItems: 4
items:
- description: DirError interrupt
- - description: DirFail interrupt
- description: DataError interrupt
- description: DataFail interrupt
+ - description: DirFail interrupt
reg:
maxItems: 1
@@ -93,7 +90,7 @@ else:
properties:
interrupts:
description: |
- Must contain entries for DirError, DirFail, DataError, DataFail signals.
+ Must contain entries for DirError, DataError, DataFail, DirFail signals.
minItems: 4
additionalProperties: false
diff --git a/drivers/soc/sifive/sifive_l2_cache.c b/drivers/soc/sifive/sifive_l2_cache.c
index 4e5e8411fbdd..59640a1d0b28 100644
--- a/drivers/soc/sifive/sifive_l2_cache.c
+++ b/drivers/soc/sifive/sifive_l2_cache.c
@@ -41,9 +41,9 @@ static struct riscv_cacheinfo_ops l2_cache_ops;
enum {
DIR_CORR = 0,
- DIR_UNCORR,
DATA_CORR,
DATA_UNCORR,
+ DIR_UNCORR,
};
#ifdef CONFIG_DEBUG_FS
@@ -194,9 +194,9 @@ static irqreturn_t l2_int_handler(int irq, void *device)
static int __init sifive_l2_init(void)
{
- int i, k, rc, intr_num, offset = 0;
struct device_node *np;
struct resource res;
+ int i, rc, intr_num;
np = of_find_matching_node(NULL, sifive_l2_ids);
if (!np)
@@ -215,27 +215,11 @@ static int __init sifive_l2_init(void)
return -ENODEV;
}
- /*
- * Only FU540 have 3 interrupts. Rest all other variants have
- * 4 interrupts (+dirfail). Therefore offset is required to skip
- * 'dirfail' interrupt entry in case of FU540
- */
- if (of_device_is_compatible(np, "sifive,fu540-c000-ccache"))
- offset = 1;
-
- g_irq[0] = irq_of_parse_and_map(np, 0);
- rc = request_irq(g_irq[0], l2_int_handler, 0, "l2_ecc", NULL);
- if (rc) {
- pr_err("L2CACHE: Could not request IRQ %d\n", g_irq[0]);
- return rc;
- }
-
- for (i = 1; i < intr_num; i++) {
- k = i + offset;
- g_irq[k] = irq_of_parse_and_map(np, i);
- rc = request_irq(g_irq[k], l2_int_handler, 0, "l2_ecc", NULL);
+ for (i = 0; i < intr_num; i++) {
+ g_irq[i] = irq_of_parse_and_map(np, i);
+ rc = request_irq(g_irq[i], l2_int_handler, 0, "l2_ecc", NULL);
if (rc) {
- pr_err("L2CACHE: Could not request IRQ %d\n", g_irq[k]);
+ pr_err("L2CACHE: Could not request IRQ %d\n", g_irq[i]);
return rc;
}
}
More information about the kernel-team
mailing list