APPLIED[G]: [SRU] [G/Unstable/OEM-5.6] [PATCH 0/1] Enable LTR for endpoints behind VMD

[Seth Forshee]

On Tue, Sep 22, 2020 at 06:42:53PM +0800, Kai-Heng Feng wrote:
> BugLink: https://bugs.launchpad.net/bugs/1896598
> 
> [Impact]
> PCIe links behind VMD may not be able to reach ASPM L1.2, because PCIe
> Link Tolenrence Reporting doesn't get programmed with a sensible value.
> 
> [Fix]
> Temporarily hardcode LTR value, which is used by Windows, for NVMe
> devices behind VMD.
> 
> [Test]
> With the patch applied, PCIe links can reach ASPM L1.2, hence the entire
> Intel SoC can reach deeper power saving state.
> 
> [Regression Potential]
> This patch targets specifically Intel Tigerlake VMD bridges, so there
> won't be any regression since they are not on the market yet.

Applied to groovy/master-next, thanks!