[SRU] [G/Unstable/OEM-5.6] [PATCH 0/1] Enable LTR for endpoints behind VMD
kai.heng.feng at canonical.com
Tue Sep 22 10:42:53 UTC 2020
PCIe links behind VMD may not be able to reach ASPM L1.2, because PCIe
Link Tolenrence Reporting doesn't get programmed with a sensible value.
Temporarily hardcode LTR value, which is used by Windows, for NVMe
devices behind VMD.
With the patch applied, PCIe links can reach ASPM L1.2, hence the entire
Intel SoC can reach deeper power saving state.
This patch targets specifically Intel Tigerlake VMD bridges, so there
won't be any regression since they are not on the market yet.
Kai-Heng Feng (1):
UBUNTU: SAUCE: PCI/ASPM: Enable LTR for endpoints behind VMD
drivers/pci/quirks.c | 49 ++++++++++++++++++++++++++++++++++++++++----
1 file changed, 45 insertions(+), 4 deletions(-)
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