[PATCH 14/23][SRU][OEM-5.6] platform/x86: intel_pmc_core: Add slp_s0_offset attribute back to tgl_reg_map

[AceLan Kao]

From: Gayatri Kammela <gayatri.kammela at intel.com>

BugLink: https://bugs.launchpad.net/bugs/1899883

If platforms such as Tiger Lake has sub-states of S0ix, then attributes
such as slps0_dbg_offset become invalid. But slp_s0_offset is still
valid as it is used to get the pmcdev_base_addr.

Hence, add back slp_s0_offset and remove slps0_dbg_offset attributes.

Cc: Chen Zhou <chenzhou10 at huawei.com>
Cc: Andy Shevchenko <andriy.shevchenko at linux.intel.com>
Cc: David E. Box <david.e.box at intel.com>
Signed-off-by: Gayatri Kammela <gayatri.kammela at intel.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko at linux.intel.com>
(cherry picked from commit 0e9c026f1b86a855cb9ab7aa270ff8db3c72015d)
Signed-off-by: AceLan Kao <acelan.kao at canonical.com>
---
 drivers/platform/x86/intel_pmc_core.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/platform/x86/intel_pmc_core.c b/drivers/platform/x86/intel_pmc_core.c
index 648db31fa1b9..af051986f31d 100644
--- a/drivers/platform/x86/intel_pmc_core.c
+++ b/drivers/platform/x86/intel_pmc_core.c
@@ -556,9 +556,9 @@ static const struct pmc_bit_map *tgl_lpm_maps[] = {
 
 static const struct pmc_reg_map tgl_reg_map = {
 	.pfear_sts = ext_tgl_pfear_map,
+	.slp_s0_offset = CNP_PMC_SLP_S0_RES_COUNTER_OFFSET,
 	.ltr_show_sts = cnp_ltr_show_map,
 	.msr_sts = msr_map,
-	.slps0_dbg_offset = CNP_PMC_SLPS0_DBG_OFFSET,
 	.ltr_ignore_offset = CNP_PMC_LTR_IGNORE_OFFSET,
 	.regmap_length = CNP_PMC_MMIO_REG_LEN,
 	.ppfear0_offset = CNP_PMC_HOST_PPFEAR0A,
-- 
2.25.1