NACK[G]: [PATCH 00/38][SRU][G/H] Add DRM support for LTTPR non-transparent link training mode

Tue Nov 24 13:13:18 UTC 2020

On 24.11.20 11:42, You-Sheng Yang wrote:
> BugLink: https://bugs.launchpad.net/bugs/1903969
> 
> [Impact]
> 
> On platforms supported DP tunneling over USB 3.2 or so, a Retimer is
> required on the host side to cover insertion loss. On such platforms the
> rtimer firmware maybe configured to use LTTPR (Link Training Tunable PHY
> Repeater) non-transparent mode only, which is only supported in drm-tip
> currently. Without LTTPR support, link training may fail with following
> error messages depending on the data path configuration:
> 
>   i915 0000:00:02.0: [drm] *ERROR* Link Training Unsuccessful
>   i915 0000:00:02.0: [drm] *ERROR* CPU pipe A FIFO underrun
> 
> [Fix]
> 
> Patchset https://www.spinics.net/lists/intel-gfx/msg248700.html
> ("drm/i915: Add support for LTTPR non-transparent link training mode")
> is required to fix this issue. It has been landed to drm-tip and will
> only included to mainline in v5.11.
> 
> Following patchsets were pulled to satisfy conflicts/link training basis:
> * Patchset https://patchwork.freedesktop.org/series/76993/ ("Plumb crtc
>   state to link training code")
> * Patch https://patchwork.freedesktop.org/series/82277/ ("drm/i915: Fix
>   TGL DKL PHY DP vswing handling")
> * Patchset https://patchwork.freedesktop.org/series/81083/ ("tgl/ehl:
>   Update voltage swing table")
> * Patchset https://patchwork.freedesktop.org/series/80404/
>   ("drm/i915/tgl: Add new voltage swing table")
> * Patchset https://patchwork.freedesktop.org/series/79265/
>   ("drm/i915/display: Implement HOBL")
> * Patchset https://patchwork.freedesktop.org/series/79481/
>   ("drm/i915/ddi: Don't rewrite DDI_BUF_CTL reg during DP link
>   training")
> * Patchset https://patchwork.freedesktop.org/series/77198/ ("drm/i915:
>   DP vswing/preemph fixes")
> * Patch https://patchwork.freedesktop.org/patch/373469/
>   ("drm/i915/display: prefer dig_port to reference intel_digital_port")
> * Patch https://patchwork.freedesktop.org/series/76917/
>   ("drm/i915: HDCP: retry link integrity check on failure")
> * Patch https://patchwork.freedesktop.org/series/77934/ ("drm/i915/tgl:
>   Add HBR and HBR2+ voltage swing table")
> * Patch https://patchwork.freedesktop.org/series/77806/ ("drm/i915/tgl:
>   Update TC DP vswing table")
> 
> [Test Case]
> 
> On Dell OptiPlex and WD19 docking station, use following steps to verify:
> 1. disconnect WD19 from OptiPlex, disconnect OptiPlex's power
> 2. attach OptiPlex's power cord
> 3. attach WD19's power cord
> 4. attach DP to WD19
> 5. attach WD19 to OptiPlex
> 6. boot up and check if boot to GUI directly
> 7. `dmesg` and check if aforementioned DRM link training error appears
> 
> [Regression Potential]
> 
> The patchsets pulled for dependency are mostly about updating voltage
> swing tables, refactoring some translation functions, along with a few
> function fixes. Aside from those, HOBL (Hours of Battery Life) is also
> pulled.
> 
> For the major part, LTTPR support, when LTTPR is either not detected or
> not supported, it will fall back to use transparent mode as it was.
> Otherwise, DP Standard recommends to use LTTPR non-transparent mode for
> link training, so this should be the right way to have best hardware
> support.
> 
> Imre Deak (8):
>   drm/i915/ddi: Don't frob the DP link scramble disabling flag
>   drm/i915/ddi: Don't rewrite DDI_BUF_CTL reg during DP link training
>   drm/i915: Fix DP link training pattern mask
>   drm/i915: Simplify the link training functions
>   drm/i915: Factor out a helper to disable the DPCD training pattern
>   drm/dp: Add LTTPR helpers
>   drm/i915: Switch to LTTPR transparent mode link training
>   drm/i915: Switch to LTTPR non-transparent mode link training
> 
> José Roberto de Souza (11):
>   drm/i915/tgl: Update TC DP vswing table
>   drm/i915/tgl: Add HBR and HBR2+ voltage swing table
>   drm/i915/display: Replace drm_i915_private in voltage swing functions
>     by intel_encoder
>   drm/i915/display: Remove port and phy from voltage swing functions
>   drm/i915/bios: Parse HOBL parameter
>   drm/i915/display: Implement HOBL
>   drm/i915/tgl: Set subplatforms
>   drm/i915/tgl: Add new voltage swing table
>   drm/i915/display/tgl: Use TGL DP tables for eDP ports without low
>     power support
>   drm/i915/display/ehl: Use EHL DP tables for eDP ports without low
>     power support
>   drm/i915/ehl: Update voltage swing table
> 
> Lucas De Marchi (1):
>   drm/i915/display: prefer dig_port to reference intel_digital_port
> 
> Oliver Barta (1):
>   drm/i915: HDCP: retry link integrity check on failure
> 
> Ville Syrjälä (17):
>   drm/i915: Fix cpt/ppt max pre-emphasis
>   drm/i915: Fix ibx max vswing/preemph
>   drm/i915: Fix ivb cpu edp vswing
>   drm/i915: Add {preemph,voltage}_max() vfuncs
>   drm/i915: Reverse preemph vs. voltage swing preference
>   drm/i915: Replace some hand rolled max()s
>   drm/i915: Fix DP_TRAIN_MAX_{PRE_EMPHASIS,SWING}_REACHED handling
>   drm/i915: Fix TGL DKL PHY DP vswing handling
>   drm/i915: s/old_crtc_state/crtc_state/
>   drm/i915: Make intel_dp_process_phy_request() static
>   drm/i915: Shove the PHY test into the hotplug work
>   drm/i915: Split ICL combo PHY buf trans per output type
>   drm/i915: Split ICL MG PHY buf trans per output type
>   drm/i915: Split EHL combo PHY buf trans per output type
>   drm/i915: Split TGL combo PHY buf trans per output type
>   drm/i915: Split TGL DKL PHY buf trans per output type
>   drm/i915: Plumb crtc_state to link training
> 
>  drivers/gpu/drm/drm_dp_helper.c               | 232 ++++-
>  drivers/gpu/drm/i915/display/intel_bios.c     |   3 +
>  drivers/gpu/drm/i915/display/intel_ddi.c      | 891 +++++++++++-------
>  drivers/gpu/drm/i915/display/intel_ddi.h      |   9 +-
>  drivers/gpu/drm/i915/display/intel_display.c  |   6 +-
>  drivers/gpu/drm/i915/display/intel_display.h  |   2 +-
>  .../drm/i915/display/intel_display_debugfs.c  |  12 +-
>  .../drm/i915/display/intel_display_power.c    |   4 +-
>  .../drm/i915/display/intel_display_types.h    |  63 +-
>  drivers/gpu/drm/i915/display/intel_dp.c       | 716 ++++++++------
>  drivers/gpu/drm/i915/display/intel_dp.h       |  19 +-
>  .../drm/i915/display/intel_dp_link_training.c | 594 ++++++++++--
>  .../drm/i915/display/intel_dp_link_training.h |  17 +-
>  drivers/gpu/drm/i915/display/intel_dp_mst.c   |  74 +-
>  drivers/gpu/drm/i915/display/intel_dp_mst.h   |   6 +-
>  drivers/gpu/drm/i915/display/intel_dpio_phy.c |  61 +-
>  drivers/gpu/drm/i915/display/intel_dpio_phy.h |   2 +
>  drivers/gpu/drm/i915/display/intel_hdcp.c     | 118 +--
>  drivers/gpu/drm/i915/display/intel_hdmi.c     | 276 +++---
>  drivers/gpu/drm/i915/display/intel_hdmi.h     |   4 +-
>  drivers/gpu/drm/i915/display/intel_lspcon.c   |   8 +-
>  drivers/gpu/drm/i915/display/intel_lspcon.h   |   2 +-
>  drivers/gpu/drm/i915/display/intel_psr.c      |   4 +-
>  drivers/gpu/drm/i915/display/intel_vbt_defs.h |   1 +
>  drivers/gpu/drm/i915/display/intel_vdsc.c     |   8 +-
>  drivers/gpu/drm/i915/i915_drv.h               |   7 +
>  drivers/gpu/drm/i915/i915_reg.h               |   8 +
>  drivers/gpu/drm/i915/intel_device_info.c      |  19 +
>  include/drm/drm_dp_helper.h                   |  62 ++
>  29 files changed, 2148 insertions(+), 1080 deletions(-)
> 

Sorry, the regression potential for this is huge. It is changing thousands lines
of code on a driver most people likely use. And about half of the changes are
marked as not yet being upstream.

-Stefan