[OEM-5.6][PATCH 31/37] drm/i915/tgl: Don't treat unslice registers as masked

[Timo Aaltonen]

From: Matt Roper <matthew.d.roper at intel.com>

BugLink: https://bugs.launchpad.net/bugs/1868727

The UNSLICE_UNIT_LEVEL_CLKGATE and UNSLICE_UNIT_LEVEL_CLKGATE2 registers
that we update in a few engine workarounds are not masked registers
(i.e., we don't have to write a mask bit in the top 16 bits when
updating one of the lower 16 bits).  As such, these workarounds should
be applied via wa_write_or() rather than wa_masked_en()

v2:
 - Rebase

Reported-by: Nick Desaulniers <ndesaulniers at google.com>
Reported-by: kernelci.org bot <bot at kernelci.org>
References: https://github.com/ClangBuiltLinux/linux/issues/918
Fixes: 50148a25f841 ("drm/i915/tgl: Move and restrict Wa_1408615072")
Fixes: 3551ff928744 ("drm/i915/gen11: Moving WAs to rcs_engine_wa_init()")
Cc: José Roberto de Souza <jose.souza at intel.com>
Signed-off-by: Matt Roper <matthew.d.roper at intel.com>
Tested-by: Nick Desaulniers <ndesaulniers at google.com>
Reviewed-by: José Roberto de Souza <jose.souza at intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20200306171139.1414649-1-matthew.d.roper@intel.com
(backported from drm-intel-next commit dbe748cd3af4a7c264a94e3e7c56a084dbd0164d)
Signed-off-by: Timo Aaltonen <timo.aaltonen at canonical.com>
---
 drivers/gpu/drm/i915/gt/intel_workarounds.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 0efa121b49d7..dee424381cd9 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -1375,8 +1375,8 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
 		wa_masked_en(wal, GEN9_ROW_CHICKEN4, GEN12_DISABLE_TDL_PUSH);
 
 		/* Wa_1408615072:tgl */
-		wa_masked_en(wal, UNSLICE_UNIT_LEVEL_CLKGATE2,
-			     VSUNIT_CLKGATE_DIS_TGL);
+		wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE2,
+			    VSUNIT_CLKGATE_DIS_TGL);
 	}
 
 	if (IS_TIGERLAKE(i915)) {
-- 
2.25.1