[OEM-5.6][PATCH 07/37] drm/i915/tgl: Add Wa_1808121037 to tgl.

Timo Aaltonen tjaalton at ubuntu.com
Tue Mar 24 14:32:36 UTC 2020

From: Rafael Antognolli <rafael.antognolli at intel.com>

BugLink: https://bugs.launchpad.net/bugs/1868727

It's not clear whether this workaround is final yet, but the BSpec
indicates that userspace needs to set bit 9 of this register on demand:

   "To avoid sporadic corruptions “Set 0x7010[9] when Depth Buffer
   Surface Format is D16_UNORM , surface type is not NULL & 1X_MSAA"

Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2501
Signed-off-by: Rafael Antognolli <rafael.antognolli at intel.com>
[mattrope: Tweaked comment while applying]
Signed-off-by: Matt Roper <matthew.d.roper at intel.com>
Reviewed-by: Matt Roper <matthew.d.roper at intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20200212191728.25227-1-rafael.antognolli@intel.com
(cherry picked from drm-intel-next commit ac204c1b34a2f0443265198a5e53795431794bd2)
Signed-off-by: Timo Aaltonen <timo.aaltonen at canonical.com>
 drivers/gpu/drm/i915/gt/intel_workarounds.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 51e1df060186..113cdc6b0ab1 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -1249,6 +1249,9 @@ static void tgl_whitelist_build(struct intel_engine_cs *engine)
 		whitelist_reg_ext(w, PS_INVOCATION_COUNT,
+		/* Wa_1808121037:tgl */
+		whitelist_reg(w, GEN7_COMMON_SLICE_CHICKEN1);

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