[PATCH 2/2][F][G][unstable] crypto: hisilicon - update SEC driver module parameter
Ike Panhc
ike.pan at canonical.com
Thu Jul 30 06:55:20 UTC 2020
BugLink: https://launchpad.net/bugs/1867900
As stress-ng running SEC engine on the Ubuntu OS,
we found that SEC only supports two threads each with one TFM
based on the default module parameter 'ctx_q_num'.
If running more threads, stress-ng will fail since it cannot
get more TFMs.
In order to fix this, we adjusted the default values
of the module parameters to support more TFMs.
Signed-off-by: Longfang Liu <liulongfang at huawei.com>
Signed-off-by: Zaibo Xu <xuzaibo at huawei.com>
(link: https://www.mail-archive.com/linux-crypto@vger.kernel.org/msg43093.html)
Signed-off-by: Ike Panhc <ike.pan at canonical.com>
---
drivers/crypto/hisilicon/sec2/sec_main.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/crypto/hisilicon/sec2/sec_main.c b/drivers/crypto/hisilicon/sec2/sec_main.c
index 2bbaf1e2dae7..1656d04b19f8 100644
--- a/drivers/crypto/hisilicon/sec2/sec_main.c
+++ b/drivers/crypto/hisilicon/sec2/sec_main.c
@@ -29,9 +29,9 @@
#define SEC_SQE_SIZE 128
#define SEC_SQ_SIZE (SEC_SQE_SIZE * QM_Q_DEPTH)
-#define SEC_PF_DEF_Q_NUM 64
+#define SEC_PF_DEF_Q_NUM 256
#define SEC_PF_DEF_Q_BASE 0
-#define SEC_CTX_Q_NUM_DEF 24
+#define SEC_CTX_Q_NUM_DEF 2
#define SEC_CTX_Q_NUM_MAX 32
#define SEC_CTRL_CNT_CLR_CE 0x301120
@@ -236,7 +236,7 @@ static const struct kernel_param_ops sec_ctx_q_num_ops = {
};
static u32 ctx_q_num = SEC_CTX_Q_NUM_DEF;
module_param_cb(ctx_q_num, &sec_ctx_q_num_ops, &ctx_q_num, 0444);
-MODULE_PARM_DESC(ctx_q_num, "Queue num in ctx (24 default, 2, 4, ..., 32)");
+MODULE_PARM_DESC(ctx_q_num, "Queue num in ctx (2 default, 2, 4, ..., 32)");
static const struct pci_device_id sec_dev_ids[] = {
{ PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, SEC_PF_PCI_DEVICE_ID) },
--
2.25.1
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