APPLIED Re: [PATCH 0/7][SRU][OEM-5.6] Support WD19TB external output on TGL platform

Timo Aaltonen tjaalton at
Wed Jul 8 05:43:59 UTC 2020

On 3.7.2020 13.10, Hsuan-Yu Lin wrote:
> BugLink:
> [Impact]
> TGL platform can't output external monitor on WD19TB docking.
> There's no screen on the external monitor.
> error in dmesg:
> [drm:intel_cpu_fifo_underrun_irq_handler [i915]] *ERROR* CPU pipe B FIFO underru
> [Fix]
> According to Intel's suggestion,
> we need this:
> Also for dependency, the following patches are landed in drm-tip
> and necessary for support TGL platform:
> * commit f4ece33f51d8 ("drm/i915/tgl+: Fix TBT DPLL fractional divider for 38.4MHz ref clock")
> * commit a6e96d6948c8 ("drm/i915/tgl+: Use the correct DP_TP_* register instances in MST encoders")
> * commit f822a79734e1 ("drm/i915/dc3co: Avoid full modeset when EXITLINE needs to be changed")
> * commit 1a7e82efaa8a ("drm/i915/tgl: Add HBR and HBR2+ voltage swing table")
> * commit 80907edcc6ed ("UBUNTU: SAUCE: drm/i915/bios: add intel_bios_hdmi_level_shift()")
> * commit 6df896896c8d ("drm/i915/tgl: Implement WA_16011163337")
> * commit cb730fe971f0 ("drm/i915/tgl: Update TC DP vswing table")

Applied to oem-5.6-next, thanks

We need to add this to groovy kernel too, at least once it's mainline.


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