[PATCH v2 16/26][SRU][U/OEM-5.10] UBUNTU: SAUCE: ath11k: disable OTP write privilege

[You-Sheng Yang]

From: Carl Huang <cjhuang at codeaurora.org>

BugLink: https://bugs.launchpad.net/bugs/1879633

Tested-on: QCA6390 hw2.0 PCI WLAN.HST.1.0.1-01740-QCAHSTSWPLZ_V2_TO_X86-1

Signed-off-by: Carl Huang <cjhuang at codeaurora.org>
Signed-off-by: Kalle Valo <kvalo at codeaurora.org>
(cherry picked from commit 86c5a1d6983e647a55448c80f94eb8f0aa97dfad
https://git.kernel.org/pub/scm/linux/kernel/git/kvalo/ath.git)
Signed-off-by: You-Sheng Yang <vicamo.yang at canonical.com>
---
 drivers/net/wireless/ath/ath11k/pci.c | 15 +++++++++++++++
 drivers/net/wireless/ath/ath11k/pci.h |  4 ++++
 2 files changed, 19 insertions(+)

diff --git a/drivers/net/wireless/ath/ath11k/pci.c b/drivers/net/wireless/ath/ath11k/pci.c
index 0b8478081f15..c058c6e9db43 100644
--- a/drivers/net/wireless/ath/ath11k/pci.c
+++ b/drivers/net/wireless/ath/ath11k/pci.c
@@ -342,6 +342,20 @@ static void ath11k_pci_clear_all_intrs(struct ath11k_base *ab)
 	ath11k_pci_write32(ab, PCIE_PCIE_INT_ALL_CLEAR, PCIE_INT_CLEAR_ALL);
 }
 
+static void ath11k_pci_set_wlaon_pwr_ctrl(struct ath11k_base *ab, bool set_vdd4blow)
+{
+	u32 val;
+
+	val = ath11k_pci_read32(ab, WLAON_QFPROM_PWR_CTRL_REG);
+
+	if (set_vdd4blow)
+		val |= QFPROM_PWR_CTRL_VDD4BLOW_MASK;
+	else
+		val &= ~QFPROM_PWR_CTRL_VDD4BLOW_MASK;
+
+	ath11k_pci_write32(ab, WLAON_QFPROM_PWR_CTRL_REG, val);
+}
+
 static void ath11k_pci_force_wake(struct ath11k_base *ab)
 {
 	int val;
@@ -358,6 +372,7 @@ static void ath11k_pci_sw_reset(struct ath11k_base *ab, bool power_on)
 	if (power_on) {
 		ath11k_pci_enable_LTSSM(ab);
 		ath11k_pci_clear_all_intrs(ab);
+		ath11k_pci_set_wlaon_pwr_ctrl(ab, false);
 		ath11k_pci_fix_l1ss(ab);
 	}
 
diff --git a/drivers/net/wireless/ath/ath11k/pci.h b/drivers/net/wireless/ath/ath11k/pci.h
index 00a2e9dd2dfc..2125cdfaa334 100644
--- a/drivers/net/wireless/ath/ath11k/pci.h
+++ b/drivers/net/wireless/ath/ath11k/pci.h
@@ -34,6 +34,10 @@
 #define PCIE_SMLH_REQ_RST_LINK_DOWN       0x2
 #define PCIE_INT_CLEAR_ALL                0xFFFFFFFF
 
+#define WLAON_QFPROM_PWR_CTRL_REG         0x01F8031C
+#define QFPROM_PWR_CTRL_VDD4BLOW_MASK     0x4
+#define QFPROM_PWR_CTRL_SHUTDOWN_MASK     0x1
+
 #define PCIE_QSERDES_COM_SYSCLK_EN_SEL_REG      0x01E0C0AC
 #define PCIE_QSERDES_COM_SYSCLK_EN_SEL_VAL      0x10
 #define PCIE_QSERDES_COM_SYSCLK_EN_SEL_MSK      0xFFFFFFFF
-- 
2.29.2