[SRU][E][PATCH 08/52] drm/i915: Tune down WARNs about TBT AUX power well enabling

You-Sheng Yang vicamo.yang at canonical.com
Wed Apr 22 14:11:31 UTC 2020

From: Imre Deak <imre.deak at intel.com>

BugLink: https://bugs.launchpad.net/bugs/1868936

The HW completion flag for the TBT AUX power well enabling/disabling
gets stuck if the firmware tears down the TBT DP tunnel before the

We shouldn't complain about the timeout, since it's expected to happen
and doesn't cause further issues. We suppress the disabling timeout
already, do the same for enabling.

- Make the debug message more precise. (José)

Cc: José Roberto de Souza <jose.souza at intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi at intel.com>
Cc: Ville Syrjälä <ville.syrjala at linux.intel.com>
Signed-off-by: Imre Deak <imre.deak at intel.com>
Reviewed-by: José Roberto de Souza <jose.souza at intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190628143635.22066-3-imre.deak@intel.com
(cherry picked from commit 28212321622d79cbab640d80d0ce0670fd9eaf72)
Signed-off-by: You-Sheng Yang <vicamo.yang at canonical.com>
 .../gpu/drm/i915/display/intel_display_power.c   | 16 +++++++++++-----
 1 file changed, 11 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index 2490a2a1b3b8..068ca8c386a9 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -269,11 +269,17 @@ static void hsw_wait_for_power_well_enable(struct drm_i915_private *dev_priv,
 	int pw_idx = power_well->desc->hsw.idx;
 	/* Timeout for PW1:10 us, AUX:not specified, other PWs:20 us. */
-	WARN_ON(intel_wait_for_register(&dev_priv->uncore,
-					regs->driver,
-					HSW_PWR_WELL_CTL_STATE(pw_idx),
-					HSW_PWR_WELL_CTL_STATE(pw_idx),
-					1));
+	if (intel_wait_for_register(&dev_priv->uncore,
+				    regs->driver,
+				    HSW_PWR_WELL_CTL_STATE(pw_idx),
+				    HSW_PWR_WELL_CTL_STATE(pw_idx),
+				    1)) {
+		DRM_DEBUG_KMS("%s power well enable timeout\n",
+			      power_well->desc->name);
+		/* An AUX timeout is expected if the TBT DP tunnel is down. */
+		WARN_ON(!power_well->desc->hsw.is_tc_tbt);
+	}
 static u32 hsw_power_well_requesters(struct drm_i915_private *dev_priv,

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