[SRU] [B/C/D] [PATCH 0/4] Fix AMD CPU MCE bug

Kai-Heng Feng kai.heng.feng at canonical.com
Wed Jul 3 07:23:02 UTC 2019

BugLink: https://bugs.launchpad.net/bugs/1796443

System doesn't boot without "mce=off".

Quote from the commit log:
"Clear the "Counter Present" bit in the Instruction Fetch bank's
MCA_MISC0 register. This will prevent enabling MCA thresholding on this
bank which will prevent the high interrupt rate due to this error."

The affected user reported these commits fix the issue.

[Regression Potential]
Low. Upstream stable commits. I don't see any regression on my
unaffected AMD systems.

Shirish S (2):
  x86/MCE/AMD: Turn off MC4_MISC thresholding on all family 0x15 models
  x86/MCE/AMD: Carve out the MC4_MISC thresholding quirk

Yazen Ghannam (2):
  x86/MCE: Add an MCE-record filtering function
  x86/MCE/AMD: Don't report L1 BTB MCA errors on some family 17h models

 arch/x86/kernel/cpu/mce/amd.c      | 62 ++++++++++++++++++++++++++++++
 arch/x86/kernel/cpu/mce/core.c     | 38 ++++--------------
 arch/x86/kernel/cpu/mce/genpool.c  |  3 ++
 arch/x86/kernel/cpu/mce/internal.h |  9 +++++
 drivers/edac/mce_amd.c             |  4 +-
 5 files changed, 84 insertions(+), 32 deletions(-)


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