[PATCH 1/2][SRU][B][C] pinctrl: cannonlake: Fix community ordering for H variant

[AceLan Kao]

From: Andy Shevchenko <andriy.shevchenko at linux.intel.com>

BugLink: https://bugs.launchpad.net/bugs/1811335

The driver was written based on an assumption that BIOS provides
unordered communities in ACPI DSDT. Nevertheless, it seems that
BIOS getting fixed before being provisioned to OxM:s.
So does driver.

BugLink: https://bugzilla.kernel.org/show_bug.cgi?id=199911
Reported-by: Marc Landolt <2009 at marclandolt.ch>
Signed-off-by: Andy Shevchenko <andriy.shevchenko at linux.intel.com>
Fixes: a663ccf0fea1 ("pinctrl: intel: Add Intel Cannon Lake PCH-H pin controller support")
Acked-by: Mika Westerberg <mika.westerberg at linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij at linaro.org>
(cherry picked from commit 17ac526824a8b5544bc2545c76f489e49c6593a2)
Signed-off-by: AceLan Kao <acelan.kao at canonical.com>
---
 drivers/pinctrl/intel/pinctrl-cannonlake.c | 8 ++------
 1 file changed, 2 insertions(+), 6 deletions(-)

diff --git a/drivers/pinctrl/intel/pinctrl-cannonlake.c b/drivers/pinctrl/intel/pinctrl-cannonlake.c
index 6243e7d95e7e..b294de0b661a 100644
--- a/drivers/pinctrl/intel/pinctrl-cannonlake.c
+++ b/drivers/pinctrl/intel/pinctrl-cannonlake.c
@@ -447,12 +447,8 @@ static const struct intel_function cnlh_functions[] = {
 static const struct intel_community cnlh_communities[] = {
 	CNL_COMMUNITY(0, 0, 50, cnlh_community0_gpps),
 	CNL_COMMUNITY(1, 51, 154, cnlh_community1_gpps),
-	/*
-	 * ACPI MMIO resources are returned in reverse order for
-	 * communities 3 and 4.
-	 */
-	CNL_COMMUNITY(3, 155, 248, cnlh_community3_gpps),
-	CNL_COMMUNITY(2, 249, 298, cnlh_community4_gpps),
+	CNL_COMMUNITY(2, 155, 248, cnlh_community3_gpps),
+	CNL_COMMUNITY(3, 249, 298, cnlh_community4_gpps),
 };
 
 static const struct intel_pinctrl_soc_data cnlh_soc_data = {
-- 
2.17.1