[PATCH 1/1][SRU][OEM-OSP1-B] drm/i915/icl: add missing GT workaround

[AceLan Kao]

From: Lionel Landwerlin <lionel.g.landwerlin at intel.com>

BugLink: https://bugs.launchpad.net/bugs/1856517

We're getting report of hang for users. Error state indicates PSD & WM
units hang. Going through the workaround database we appear to be
missing this permanent workaround.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
(backported from commit ebfb27a7c07e35110a484f7a1ba7406f75b8bf98
https://github.com/djdeath/linux.git wip/gen11-fixes)
Signed-off-by: AceLan Kao <acelan.kao at canonical.com>
---
 drivers/gpu/drm/i915/i915_reg.h          | 3 +++
 drivers/gpu/drm/i915/intel_workarounds.c | 6 ++++++
 2 files changed, 9 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index a661c2136478..cb829f44f683 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7609,6 +7609,9 @@ enum {
 #define GEN11_COMMON_SLICE_CHICKEN3		_MMIO(0x7304)
   #define GEN11_BLEND_EMB_FIX_DISABLE_IN_RCC	(1 << 11)
 
+#define GEN11_SCCGCTL _MMIO(0x94e4)
+# define  GEN11_SCCGCTL_PSD_CLOCK_GATING_DISABLE (1 << 5)
+
 #define HIZ_CHICKEN					_MMIO(0x7018)
 # define CHV_HZ_8X8_MODE_IN_1X				(1 << 15)
 # define BDW_HIZ_POWER_COMPILER_CLOCK_GATING_DISABLE	(1 << 3)
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
index 3ca0764b218d..e2c0d88e5894 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -520,6 +520,12 @@ static void icl_ctx_workarounds_init(struct intel_engine_cs *engine)
 		 I915_READ(GEN8_L3CNTLREG) |
 		 GEN8_ERRDETBCTRL);
 
+	/* Wa_1407352427:icl */
+	wa_write(wal,
+		 GEN11_COMMON_SLICE_CHICKEN3,
+		 I915_READ(GEN11_COMMON_SLICE_CHICKEN3) |
+		 GEN11_SCCGCTL_PSD_CLOCK_GATING_DISABLE);
+
 	/* Wa_1604370585:icl (pre-prod)
 	 * Formerly known as WaPushConstantDereferenceHoldDisable
 	 */
-- 
2.17.1