ACK: [PATCH] perf vendor events arm64: Update ThunderX2 implementation defined pmu core events

[Stefan Bader]

On 09.10.2018 16:52, Manoj Iyer wrote:
> From: Ganapatrao Kulkarni <ganapatrao.kulkarni at cavium.com>
> 
> BugLink: http://launchpad.net/bugs/1796904
> 
> Signed-off-by: Ganapatrao Kulkarni <ganapatrao.kulkarni at cavium.com>
> Cc: Alexander Shishkin <alexander.shishkin at linux.intel.com>
> Cc: Ganapatrao Kulkarni <gklkml16 at gmail.com>
> Cc: Jan Glauber <jan.glauber at cavium.com>
> Cc: Jayachandran C <jnair at caviumnetworks.com>
> Cc: Jiri Olsa <jolsa at redhat.com>
> Cc: linux-arm-kernel at lists.infradead.org
> Cc: Mark Rutland <mark.rutland at arm.com>
> Cc: Namhyung Kim <namhyung at kernel.org>
> Cc: Peter Zijlstra <peterz at infradead.org>
> Cc: Robert Richter <robert.richter at cavium.com>
> Cc: Vadim Lomovtsev <vadim.lomovtsev at cavium.com>
> Cc: Will Deacon <will.deacon at arm.com>
> Link: http://lkml.kernel.org/r/20180731100251.23575-1-ganapatrao.kulkarni@cavium.com
> Signed-off-by: Arnaldo Carvalho de Melo <acme at redhat.com>
> (cherry picked from commit b9b77222d4ff6b5bb8f5d87fca20de0910618bb9)
> Signed-off-by: Manoj Iyer <manoj.iyer at canonical.com>
Acked-by: Stefan Bader <stefan.bader at canonical.com>
> ---
Looks to be safely out of the way of most things...

>  .../arm64/cavium/thunderx2/core-imp-def.json  | 87 ++++++++++++++++++-
>  1 file changed, 84 insertions(+), 3 deletions(-)
> 
> diff --git a/tools/perf/pmu-events/arch/arm64/cavium/thunderx2/core-imp-def.json b/tools/perf/pmu-events/arch/arm64/cavium/thunderx2/core-imp-def.json
> index bc03c06c3918..752e47eb6977 100644
> --- a/tools/perf/pmu-events/arch/arm64/cavium/thunderx2/core-imp-def.json
> +++ b/tools/perf/pmu-events/arch/arm64/cavium/thunderx2/core-imp-def.json
> @@ -11,6 +11,21 @@
>      {
>          "ArchStdEvent": "L1D_CACHE_REFILL_WR",
>      },
> +    {
> +        "ArchStdEvent": "L1D_CACHE_REFILL_INNER",
> +    },
> +    {
> +        "ArchStdEvent": "L1D_CACHE_REFILL_OUTER",
> +    },
> +    {
> +        "ArchStdEvent": "L1D_CACHE_WB_VICTIM",
> +    },
> +    {
> +        "ArchStdEvent": "L1D_CACHE_WB_CLEAN",
> +    },
> +    {
> +        "ArchStdEvent": "L1D_CACHE_INVAL",
> +    },
>      {
>          "ArchStdEvent": "L1D_TLB_REFILL_RD",
>      },
> @@ -23,10 +38,76 @@
>      {
>          "ArchStdEvent": "L1D_TLB_WR",
>      },
> +    {
> +        "ArchStdEvent": "L2D_TLB_REFILL_RD",
> +    },
> +    {
> +        "ArchStdEvent": "L2D_TLB_REFILL_WR",
> +    },
> +    {
> +        "ArchStdEvent": "L2D_TLB_RD",
> +    },
> +    {
> +        "ArchStdEvent": "L2D_TLB_WR",
> +    },
>      {
>          "ArchStdEvent": "BUS_ACCESS_RD",
> -   },
> -   {
> +    },
> +    {
>          "ArchStdEvent": "BUS_ACCESS_WR",
> -   }
> +    },
> +    {
> +        "ArchStdEvent": "MEM_ACCESS_RD",
> +    },
> +    {
> +        "ArchStdEvent": "MEM_ACCESS_WR",
> +    },
> +    {
> +        "ArchStdEvent": "UNALIGNED_LD_SPEC",
> +    },
> +    {
> +        "ArchStdEvent": "UNALIGNED_ST_SPEC",
> +    },
> +    {
> +        "ArchStdEvent": "UNALIGNED_LDST_SPEC",
> +    },
> +    {
> +        "ArchStdEvent": "EXC_UNDEF",
> +    },
> +    {
> +        "ArchStdEvent": "EXC_SVC",
> +    },
> +    {
> +        "ArchStdEvent": "EXC_PABORT",
> +    },
> +    {
> +        "ArchStdEvent": "EXC_DABORT",
> +    },
> +    {
> +        "ArchStdEvent": "EXC_IRQ",
> +    },
> +    {
> +        "ArchStdEvent": "EXC_FIQ",
> +    },
> +    {
> +        "ArchStdEvent": "EXC_SMC",
> +    },
> +    {
> +        "ArchStdEvent": "EXC_HVC",
> +    },
> +    {
> +        "ArchStdEvent": "EXC_TRAP_PABORT",
> +    },
> +    {
> +        "ArchStdEvent": "EXC_TRAP_DABORT",
> +    },
> +    {
> +        "ArchStdEvent": "EXC_TRAP_OTHER",
> +    },
> +    {
> +        "ArchStdEvent": "EXC_TRAP_IRQ",
> +    },
> +    {
> +        "ArchStdEvent": "EXC_TRAP_FIQ",
> +    }
>  ]
> 


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