[SRU][Xenial][PATCH 2/6] UBUNTU: SAUCE: x86/cpufeatures: Move CPUID_7_EDX CPUID bits to word 18
Juerg Haefliger
juerg.haefliger at canonical.com
Wed May 30 11:38:13 UTC 2018
CVE-2018-3639 (x86)
It's ok to have holes in CPU feature bits array, so move the CPUID_7_EDX
bits from word 16 to word 18 to match upstream. Primarily to avoid
confusion and conflicts with future backports/cherry-picks.
Fixes: e8e6c1d5c153 ("x86/cpufeatures: Add CPUID_7_EDX CPUID leaf")
Signed-off-by: Juerg Haefliger <juergh at canonical.com>
---
arch/x86/include/asm/cpufeature.h | 10 ++++++++--
arch/x86/include/asm/cpufeatures.h | 12 ++++++------
arch/x86/include/asm/disabled-features.h | 2 ++
arch/x86/include/asm/required-features.h | 2 ++
4 files changed, 18 insertions(+), 8 deletions(-)
diff --git a/arch/x86/include/asm/cpufeature.h b/arch/x86/include/asm/cpufeature.h
index b28546a6005e..27d03fa990e0 100644
--- a/arch/x86/include/asm/cpufeature.h
+++ b/arch/x86/include/asm/cpufeature.h
@@ -26,6 +26,8 @@ enum cpuid_leafs
CPUID_8000_0008_EBX,
CPUID_6_EAX,
CPUID_8000_000A_EDX,
+ CPUID_7_ECX,
+ CPUID_8000_0007_EBX,
CPUID_7_EDX,
};
@@ -65,7 +67,9 @@ extern const char * const x86_bug_flags[NBUGINTS*32];
(((bit)>>5)==13 && (1UL<<((bit)&31) & REQUIRED_MASK13)) || \
(((bit)>>5)==14 && (1UL<<((bit)&31) & REQUIRED_MASK14)) || \
(((bit)>>5)==15 && (1UL<<((bit)&31) & REQUIRED_MASK15)) || \
- (((bit)>>5)==16 && (1UL<<((bit)&31) & REQUIRED_MASK16)) )
+ (((bit)>>5)==16 && (1UL<<((bit)&31) & REQUIRED_MASK16)) || \
+ (((bit)>>5)==17 && (1UL<<((bit)&31) & REQUIRED_MASK17)) || \
+ (((bit)>>5)==18 && (1UL<<((bit)&31) & REQUIRED_MASK18)) )
#define DISABLED_MASK_BIT_SET(bit) \
( (((bit)>>5)==0 && (1UL<<((bit)&31) & DISABLED_MASK0 )) || \
@@ -84,7 +88,9 @@ extern const char * const x86_bug_flags[NBUGINTS*32];
(((bit)>>5)==13 && (1UL<<((bit)&31) & DISABLED_MASK13)) || \
(((bit)>>5)==14 && (1UL<<((bit)&31) & DISABLED_MASK14)) || \
(((bit)>>5)==15 && (1UL<<((bit)&31) & DISABLED_MASK15)) || \
- (((bit)>>5)==16 && (1UL<<((bit)&31) & DISABLED_MASK16)) )
+ (((bit)>>5)==16 && (1UL<<((bit)&31) & DISABLED_MASK16)) || \
+ (((bit)>>5)==17 && (1UL<<((bit)&31) & DISABLED_MASK17)) || \
+ (((bit)>>5)==18 && (1UL<<((bit)&31) & DISABLED_MASK18)) )
#define cpu_has(c, bit) \
(__builtin_constant_p(bit) && REQUIRED_MASK_BIT_SET(bit) ? 1 : \
diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h
index 8db6b345e199..60062f510648 100644
--- a/arch/x86/include/asm/cpufeatures.h
+++ b/arch/x86/include/asm/cpufeatures.h
@@ -12,7 +12,7 @@
/*
* Defines x86 CPU feature bits
*/
-#define NCAPINTS 17 /* N 32-bit words worth of info */
+#define NCAPINTS 19 /* N 32-bit words worth of info */
#define NBUGINTS 1 /* N 32-bit bug flags */
/*
@@ -297,11 +297,11 @@
#define X86_FEATURE_PFTHRESHOLD (15*32+12) /* pause filter threshold */
#define X86_FEATURE_AVIC (15*32+13) /* Virtual Interrupt Controller */
-/* Intel-defined CPU features, CPUID level 0x00000007:0 (EDX), word 16 */
-#define X86_FEATURE_SPEC_CTRL (16*32+26) /* "" Speculation Control (IBRS + IBPB) */
-#define X86_FEATURE_INTEL_STIBP (16*32+27) /* "" Single Thread Indirect Branch Predictors */
-#define X86_FEATURE_ARCH_CAPABILITIES (16*32+29) /* IA32_ARCH_CAPABILITIES MSR (Intel) */
-#define X86_FEATURE_SPEC_CTRL_SSBD (16*32+31) /* "" Speculative Store Bypass Disable */
+/* Intel-defined CPU features, CPUID level 0x00000007:0 (EDX), word 18 */
+#define X86_FEATURE_SPEC_CTRL (18*32+26) /* "" Speculation Control (IBRS + IBPB) */
+#define X86_FEATURE_INTEL_STIBP (18*32+27) /* "" Single Thread Indirect Branch Predictors */
+#define X86_FEATURE_ARCH_CAPABILITIES (18*32+29) /* IA32_ARCH_CAPABILITIES MSR (Intel) */
+#define X86_FEATURE_SPEC_CTRL_SSBD (18*32+31) /* "" Speculative Store Bypass Disable */
/*
* BUG word(s)
diff --git a/arch/x86/include/asm/disabled-features.h b/arch/x86/include/asm/disabled-features.h
index d1865655c975..c06553e2bae4 100644
--- a/arch/x86/include/asm/disabled-features.h
+++ b/arch/x86/include/asm/disabled-features.h
@@ -56,5 +56,7 @@
#define DISABLED_MASK14 0
#define DISABLED_MASK15 0
#define DISABLED_MASK16 0
+#define DISABLED_MASK17 0
+#define DISABLED_MASK18 0
#endif /* _ASM_X86_DISABLED_FEATURES_H */
diff --git a/arch/x86/include/asm/required-features.h b/arch/x86/include/asm/required-features.h
index 4916144e3c42..4660863b6f6b 100644
--- a/arch/x86/include/asm/required-features.h
+++ b/arch/x86/include/asm/required-features.h
@@ -99,5 +99,7 @@
#define REQUIRED_MASK14 0
#define REQUIRED_MASK15 0
#define REQUIRED_MASK16 0
+#define REQUIRED_MASK17 0
+#define REQUIRED_MASK18 0
#endif /* _ASM_X86_REQUIRED_FEATURES_H */
--
2.17.0
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