[PATCH 2/3] PCI: Mark Cavium CN8xxx to avoid bus reset

[Manoj Iyer]

From: David Daney <david.daney at cavium.com>

Root ports of cn8xxx do not function after bus reset when used with some
e1000e and LSI HBA devices.  Add a quirk to prevent bus reset on these root
ports.

BugLink: https://launchpad.net/bugs/1770254

Signed-off-by: David Daney <david.daney at cavium.com>
[jglauber at cavium.com: fixed typo and whitespaces]
Signed-off-by: Jan Glauber <jglauber at cavium.com>
Signed-off-by: Bjorn Helgaas <bhelgaas at google.com>
Reviewed-by: Alex Williamson <alex.williamson at redhat.com>
(cherry picked from commit 822155100e589f2a4891b3b2db2f901824d47e69)
Signed-off-by: Manoj Iyer <manoj.iyer at canonical.com>
---
 drivers/pci/quirks.c | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
index 99eec22d99b7..9dcd5ed5a05b 100644
--- a/drivers/pci/quirks.c
+++ b/drivers/pci/quirks.c
@@ -3380,6 +3380,13 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0032, quirk_no_bus_reset);
 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x003c, quirk_no_bus_reset);
 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0033, quirk_no_bus_reset);
 
+/*
+ * Root port on some Cavium CN8xxx chips do not successfully complete a bus
+ * reset when used with certain child devices.  After the reset, config
+ * accesses to the child may fail.
+ */
+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CAVIUM, 0xa100, quirk_no_bus_reset);
+
 static void quirk_no_pm_reset(struct pci_dev *dev)
 {
 	/*
-- 
2.17.0