ACK/cmnt: [PATCH][OEM][Artful] drm/i915: Apply Display WA #1183 on skl, kbl, and cfl

Stefan Bader stefan.bader at canonical.com
Wed Mar 28 12:39:10 UTC 2018


On 28.03.2018 05:20, AceLan Kao wrote:
> From: Lucas De Marchi <lucas.demarchi at intel.com>
> 
> BugLink: https://launchpad.net/bugs/1759188
> 
> Display WA #1183 was recently added to workaround
> "Failures when enabling DPLL0 with eDP link rate 2.16
> or 4.32 GHz and CD clock frequency 308.57 or 617.14 MHz
> (CDCLK_CTL CD Frequency Select 10b or 11b) used in this
>  enabling or in previous enabling."
> 
> This workaround was designed to minimize the impact only
> to save the bad case with that link rates. But HW engineers
> indicated that it should be safe to apply broadly, although
> they were expecting the DPLL0 link rate to be unchanged on
> runtime.
> 
> We need to cover 2 cases: when we are in fact enabling DPLL0
> and when we are just changing the frequency with small
> differences.
> 
> This is based on previous patch by Rodrigo Vivi with suggestions
> from Ville Syrjälä.
> 
> Cc: Arthur J Runyan <arthur.j.runyan at intel.com>
> Cc: Ville Syrjälä <ville.syrjala at linux.intel.com>
> Cc: Rodrigo Vivi <rodrigo.vivi at intel.com>
> Cc: stable at vger.kernel.org
> Signed-off-by: Lucas De Marchi <lucas.demarchi at intel.com>
> Reviewed-by: Ville Syrjälä <ville.syrjala at linux.intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi at intel.com>
> Link: https://patchwork.freedesktop.org/patch/msgid/20171204232210.4958-1-lucas.demarchi@intel.com
> (cherry picked from commit 53421c2fe99ce16838639ad89d772d914a119a49)
> [ Lucas: Backport to 4.15 adding back variable that has been removed on
>   commits not meant to be backported ]
> Signed-off-by: Jani Nikula <jani.nikula at intel.com>
> Link: https://patchwork.freedesktop.org/patch/msgid/20180102201837.6812-1-lucas.demarchi@intel.com
> 
> (cherry picked from commit 30414f3010aff95ffdb6bed7b9dce62cde94fdc7)
> Signed-off-by: AceLan Kao <acelan.kao at canonical.com>
Acked-by: Stefan Bader <stefan.bader at canonical.com>

> ---

This seems to have been part of 4.15-rc7 so should be included in Bionic already.

>  drivers/gpu/drm/i915/i915_reg.h         |  2 ++
>  drivers/gpu/drm/i915/intel_cdclk.c      | 35 ++++++++++++++++++++++++---------
>  drivers/gpu/drm/i915/intel_runtime_pm.c | 10 ++++++++++
>  3 files changed, 38 insertions(+), 9 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 91b1e92..c53d369 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -6748,6 +6748,7 @@ enum {
>  #define  RESET_PCH_HANDSHAKE_ENABLE	(1<<4)
>  
>  #define GEN8_CHICKEN_DCPR_1		_MMIO(0x46430)
> +#define   SKL_SELECT_ALTERNATE_DC_EXIT	(1<<30)
>  #define   MASK_WAKEMEM			(1<<13)
>  
>  #define SKL_DFSM			_MMIO(0x51000)
> @@ -8256,6 +8257,7 @@ enum {
>  #define  BXT_CDCLK_CD2X_DIV_SEL_2	(2<<22)
>  #define  BXT_CDCLK_CD2X_DIV_SEL_4	(3<<22)
>  #define  BXT_CDCLK_CD2X_PIPE(pipe)	((pipe)<<20)
> +#define  CDCLK_DIVMUX_CD_OVERRIDE	(1<<19)
>  #define  BXT_CDCLK_CD2X_PIPE_NONE	BXT_CDCLK_CD2X_PIPE(3)
>  #define  BXT_CDCLK_SSA_PRECHARGE_ENABLE	(1<<16)
>  #define  CDCLK_FREQ_DECIMAL_MASK	(0x7ff)
> diff --git a/drivers/gpu/drm/i915/intel_cdclk.c b/drivers/gpu/drm/i915/intel_cdclk.c
> index b156032..7ca6f4f 100644
> --- a/drivers/gpu/drm/i915/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/intel_cdclk.c
> @@ -856,16 +856,10 @@ static void skl_set_preferred_cdclk_vco(struct drm_i915_private *dev_priv,
>  
>  static void skl_dpll0_enable(struct drm_i915_private *dev_priv, int vco)
>  {
> -	int min_cdclk = skl_calc_cdclk(0, vco);
>  	u32 val;
>  
>  	WARN_ON(vco != 8100000 && vco != 8640000);
>  
> -	/* select the minimum CDCLK before enabling DPLL 0 */
> -	val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_cdclk);
> -	I915_WRITE(CDCLK_CTL, val);
> -	POSTING_READ(CDCLK_CTL);
> -
>  	/*
>  	 * We always enable DPLL0 with the lowest link rate possible, but still
>  	 * taking into account the VCO required to operate the eDP panel at the
> @@ -919,7 +913,7 @@ static void skl_set_cdclk(struct drm_i915_private *dev_priv,
>  {
>  	int cdclk = cdclk_state->cdclk;
>  	int vco = cdclk_state->vco;
> -	u32 freq_select, pcu_ack;
> +	u32 freq_select, pcu_ack, cdclk_ctl;
>  	int ret;
>  
>  	WARN_ON((cdclk == 24000) != (vco == 0));
> @@ -936,7 +930,7 @@ static void skl_set_cdclk(struct drm_i915_private *dev_priv,
>  		return;
>  	}
>  
> -	/* set CDCLK_CTL */
> +	/* Choose frequency for this cdclk */
>  	switch (cdclk) {
>  	case 450000:
>  	case 432000:
> @@ -964,10 +958,33 @@ static void skl_set_cdclk(struct drm_i915_private *dev_priv,
>  	    dev_priv->cdclk.hw.vco != vco)
>  		skl_dpll0_disable(dev_priv);
>  
> +	cdclk_ctl = I915_READ(CDCLK_CTL);
> +
> +	if (dev_priv->cdclk.hw.vco != vco) {
> +		/* Wa Display #1183: skl,kbl,cfl */
> +		cdclk_ctl &= ~(CDCLK_FREQ_SEL_MASK | CDCLK_FREQ_DECIMAL_MASK);
> +		cdclk_ctl |= freq_select | skl_cdclk_decimal(cdclk);
> +		I915_WRITE(CDCLK_CTL, cdclk_ctl);
> +	}
> +
> +	/* Wa Display #1183: skl,kbl,cfl */
> +	cdclk_ctl |= CDCLK_DIVMUX_CD_OVERRIDE;
> +	I915_WRITE(CDCLK_CTL, cdclk_ctl);
> +	POSTING_READ(CDCLK_CTL);
> +
>  	if (dev_priv->cdclk.hw.vco != vco)
>  		skl_dpll0_enable(dev_priv, vco);
>  
> -	I915_WRITE(CDCLK_CTL, freq_select | skl_cdclk_decimal(cdclk));
> +	/* Wa Display #1183: skl,kbl,cfl */
> +	cdclk_ctl &= ~(CDCLK_FREQ_SEL_MASK | CDCLK_FREQ_DECIMAL_MASK);
> +	I915_WRITE(CDCLK_CTL, cdclk_ctl);
> +
> +	cdclk_ctl |= freq_select | skl_cdclk_decimal(cdclk);
> +	I915_WRITE(CDCLK_CTL, cdclk_ctl);
> +
> +	/* Wa Display #1183: skl,kbl,cfl */
> +	cdclk_ctl &= ~CDCLK_DIVMUX_CD_OVERRIDE;
> +	I915_WRITE(CDCLK_CTL, cdclk_ctl);
>  	POSTING_READ(CDCLK_CTL);
>  
>  	/* inform PCU of the change */
> diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
> index 5eb9c5e..efe8227 100644
> --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> @@ -769,6 +769,11 @@ void gen9_enable_dc5(struct drm_i915_private *dev_priv)
>  
>  	DRM_DEBUG_KMS("Enabling DC5\n");
>  
> +	/* Wa Display #1183: skl,kbl,cfl */
> +	if (IS_GEN9_BC(dev_priv))
> +		I915_WRITE(GEN8_CHICKEN_DCPR_1, I915_READ(GEN8_CHICKEN_DCPR_1) |
> +			   SKL_SELECT_ALTERNATE_DC_EXIT);
> +
>  	gen9_set_dc_state(dev_priv, DC_STATE_EN_UPTO_DC5);
>  }
>  
> @@ -796,6 +801,11 @@ void skl_disable_dc6(struct drm_i915_private *dev_priv)
>  {
>  	DRM_DEBUG_KMS("Disabling DC6\n");
>  
> +	/* Wa Display #1183: skl,kbl,cfl */
> +	if (IS_GEN9_BC(dev_priv))
> +		I915_WRITE(GEN8_CHICKEN_DCPR_1, I915_READ(GEN8_CHICKEN_DCPR_1) |
> +			   SKL_SELECT_ALTERNATE_DC_EXIT);
> +
>  	gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
>  }
>  
> 


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