[SRU][Artful][PATCH 0/1] powerpc/64s: Initialize ISAv3 MMU registers before setting partition table

Joseph Salisbury joseph.salisbury at canonical.com
Mon Feb 5 20:50:37 UTC 2018


BugLink: http://bugs.launchpad.net/bugs/1736145

== SRU Justification ==
Kexec can leave MMU registers set, PIDR in particular, when booting the
new kernel. The boot sequence does not zero PIDR ever, and it only gets
changed as CPUs first switch to userspace processes. This can leave a
window where speculative accesses from a CPU to quadrant 0 can pick up
translations in the partition table that may be set up for processes
running on other CPUs. These cached translations will not be involved in
the invalidation protocol, so we can end with stable TLB and PWC.

This commit was included in mailine as of v4.15-rc5 and fixes commit 7e381c0ff618.

This commit has already landed in Bionic via upstream stable updates.

== Fix ==
commit 371b80447ff33ddac392c189cf884a5a3e18faeb
Author: Nicholas Piggin <npiggin at gmail.com>
Date:   Wed Dec 6 18:21:14 2017 +1000

    powerpc/64s: Initialize ISAv3 MMU registers before setting partition table

== Regression Potential ==
Low. This fix is specific to powerpc.  It has also been cc'd to upstream stable, 
so it has had additional upstream review.


== Test Case ==
A test kernel was built with this patch and tested by the original bug reporter.
The bug reporter states the test kernel resolved the bug.

Nicholas Piggin (1):
  powerpc/64s: Initialize ISAv3 MMU registers before setting partition
    table

 arch/powerpc/kernel/cpu_setup_power.S | 2 ++
 1 file changed, 2 insertions(+)

-- 
2.7.4





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