[SRU][Zesty][PATCH 2/2] powerpc/perf: POWER9 PMU stops after idle workaround

Joseph Salisbury joseph.salisbury at canonical.com
Wed Sep 20 15:17:18 UTC 2017

From: Nicholas Piggin <npiggin at gmail.com>

BugLink: http://bugs.launchpad.net/bugs/1716491

POWER9 DD2 PMU can stop after a state-loss idle in some conditions.

A solution is to set then clear MMCRA[60] after wake from state-loss
idle. MMCRA[60] is a non-architected bit, see the user manual for

Signed-off-by: Nicholas Piggin <npiggin at gmail.com>
Acked-by: Madhavan Srinivasan <maddy at linux.vnet.ibm.com>
Reviewed-by: Vaidyanathan Srinivasan <svaidy at linux.vnet.ibm.com>
Acked-by: Anton Blanchard <anton at samba.org>
Signed-off-by: Michael Ellerman <mpe at ellerman.id.au>
(cherry picked from commit 09539f9b123652e969894d6299ae0df2fe12cb5d)
Signed-off-by: Joseph Salisbury <joseph.salisbury at canonical.com>
 arch/powerpc/kernel/idle_book3s.S | 8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/arch/powerpc/kernel/idle_book3s.S b/arch/powerpc/kernel/idle_book3s.S
index e003fb9..6be7cd4 100644
--- a/arch/powerpc/kernel/idle_book3s.S
+++ b/arch/powerpc/kernel/idle_book3s.S
 	 * Workaround for POWER9, if we lost resources, the ERAT
 	 * might have been mixed up and needs flushing. We also need
-	 * to reload MMCR0 (see comment above).
+	 * to reload MMCR0 (see comment above). We also need to set
+	 * then clear bit 60 in MMCRA to ensure the PMU starts running.
 	blt	cr3,1f
 	ld	r1,PACAR1(r13)
+	mfspr	r4,SPRN_MMCRA
+	ori	r4,r4,(1 << (63-60))
+	mtspr	SPRN_MMCRA,r4
+	xori	r4,r4,(1 << (63-60))
+	mtspr	SPRN_MMCRA,r4
 	ld	r4,_MMCR0(r1)
 	mtspr	SPRN_MMCR0,r4

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