APPLIED: [SRU][Artful][PATCH 0/2] Fixes for LP:1721070

Seth Forshee seth.forshee at
Mon Oct 16 14:33:13 UTC 2017

On Fri, Oct 06, 2017 at 01:26:04PM -0400, Joseph Salisbury wrote:
> BugLink:
> == SRU Justification ==
> POWER9 DD2.1 and earlier has an issue where some cache inhibited
> vector load will return bad data. The fix is two part, one
> firmware/microcode part triggers HMI interrupts when hitting such
> loads, the other part is commit 5080332c2c89 from linux-next which then 
> emulates the instructions in Linux.
> The affected instructions are limited to lxvd2x, lxvw4x, lxvb16x and
> lxvh8x.
> Commit ccd3cd361341 is needed as a prereq, and is in mainline as of 4.14-rc1.
> Commit 5080332c2c89 is still in linux-next.  Both commts are clean cherry
> picks in Artful.  This fix is also need in Zesty, but Zesty needs an addition
> prereq, so a seperate SRU request will be sent.
> == Fixes ==
> ccd3cd361341 ("powerpc/mce: Move 64-bit machine check code into mce.c")
> 5080332c2c89 ("powerpc/64s: Add workaround for P9 vector CI load issue") 
> == Regression Potential ==
> These commits are specific to powerpc and have been tested by IBM.
> == Test Case == 
> A test kernel was built with these patches and tested by the original bug reporter.
> The bug reporter states the test kernel resolved the bug.

Applied to artful/master-next. Also applied patch 2 to unstable/master.

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