[ZESTY] [PATCH 29/33] powerpc/64: Invalidate process table caching after setting process table

Breno Leitao leitao at debian.org
Tue Mar 28 16:54:41 UTC 2017

From: Paul Mackerras <paulus at ozlabs.org>

BugLink: https://bugs.launchpad.net/ubuntu/+source/linux/+bug/1675806

The POWER9 MMU reads and caches entries from the process table.
When we kexec from one kernel to another, the second kernel sets
its process table pointer but doesn't currently do anything to
make the CPU invalidate any cached entries from the old process table.
This adds a tlbie (TLB invalidate entry) instruction with parameters
to invalidate caching of the process table after the new process
table is installed.

Signed-off-by: Paul Mackerras <paulus at ozlabs.org>
Signed-off-by: Michael Ellerman <mpe at ellerman.id.au>
(cherry picked from commit 7a70d7288c926ae88e0c773fbb506aa374e99c2d)
Signed-off-by: Breno Leitao <breno.leitao at gmail.com>
 arch/powerpc/mm/pgtable-radix.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/arch/powerpc/mm/pgtable-radix.c b/arch/powerpc/mm/pgtable-radix.c
index cb66c2ba469e..8e11802d9079 100644
--- a/arch/powerpc/mm/pgtable-radix.c
+++ b/arch/powerpc/mm/pgtable-radix.c
@@ -185,6 +185,10 @@ static void __init radix_init_pgtable(void)
 	register_process_table(__pa(process_tb), 0, PRTB_SIZE_SHIFT - 12);
 	pr_info("Process table %p and radix root for kernel: %p\n", process_tb, init_mm.pgd);
+	asm volatile("ptesync" : : : "memory");
+	asm volatile(PPC_TLBIE_5(%0,%1,2,1,1) : :
+		     "r" (TLBIEL_INVAL_SET_LPID), "r" (0));
+	asm volatile("eieio; tlbsync; ptesync" : : : "memory");
 static void __init radix_init_partition_table(void)

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