[PATCH 1/2] powerpc/mm: Fix no execute fault handling on pre-POWER5

[Tim Gardner]

From: Balbir Singh <bsingharora at gmail.com>

BugLink: http://bugs.launchpad.net/bugs/1664564

Aneesh/Ben reported that the change to do_page_fault() we made in commit
1d18ad026844 ("powerpc/mm: Detect instruction fetch denied and report")
needs to handle the case where CPU_FTR_COHERENT_ICACHE is missing but we
have CPU_FTR_NOEXECUTE. In those cases the check added for
SRR1_ISI_N_OR_G might trigger a false positive.

This patch adds a check for CPU_FTR_COHERENT_ICACHE in addition to the
MSR value.

Fixes: 1d18ad026844 ("powerpc/mm: Detect instruction fetch denied and report")
Reported-by: Aneesh Kumar K.V <aneesh.kumar at linux.vnet.ibm.com>
Acked-by: Benjamin Herrenschmidt <benh at kernel.crashing.org>
Signed-off-by: Balbir Singh <bsingharora at gmail.com>
Signed-off-by: Michael Ellerman <mpe at ellerman.id.au>
(cherry picked from commit 0ab5171b8971282d7562b77f9b14137a827117fc)
Signed-off-by: Tim Gardner <tim.gardner at canonical.com>
---
 arch/powerpc/mm/fault.c | 10 +++++++++-
 1 file changed, 9 insertions(+), 1 deletion(-)

diff --git a/arch/powerpc/mm/fault.c b/arch/powerpc/mm/fault.c
index 18bbb9e..242c9b0 100644
--- a/arch/powerpc/mm/fault.c
+++ b/arch/powerpc/mm/fault.c
@@ -392,8 +392,16 @@ good_area:
 	if (is_exec) {
 		/*
 		 * An execution fault + no execute ?
+		 *
+		 * On CPUs that don't have CPU_FTR_COHERENT_ICACHE we
+		 * deliberately create NX mappings, and use the fault to do the
+		 * cache flush. This is usually handled in hash_page_do_lazy_icache()
+		 * but we could end up here if that races with a concurrent PTE
+		 * update. In that case we need to fall through here to the VMA
+		 * check below.
 		 */
-		if (regs->msr & SRR1_ISI_N_OR_G)
+		if (cpu_has_feature(CPU_FTR_COHERENT_ICACHE) &&
+			(regs->msr & SRR1_ISI_N_OR_G))
 			goto bad_area;
 
 		/*
-- 
2.7.4