[3.19.y-ckt stable] Patch "intel_pstate: set BYT MSR with wrmsrl_on_cpu()" has been added to staging queue

[Kamal Mostafa]

This is a note to let you know that I have just added a patch titled

    intel_pstate: set BYT MSR with wrmsrl_on_cpu()

to the linux-3.19.y-queue branch of the 3.19.y-ckt extended stable tree 
which can be found at:

    http://kernel.ubuntu.com/git/ubuntu/linux.git/log/?h=linux-3.19.y-queue

This patch is scheduled to be released in version 3.19.y-ckt4.

If you, or anyone else, feels it should not be added to this tree, please 
reply to this email.

For more information about the 3.19.y-ckt tree, see
https://wiki.ubuntu.com/Kernel/Dev/ExtendedStable

Thanks.
-Kamal

------

>From d0fe305dc9203b40a874893d6c8502fde7fda764 Mon Sep 17 00:00:00 2001
From: Joe Konno <joe.konno at intel.com>
Date: Tue, 12 May 2015 07:59:42 -0700
Subject: intel_pstate: set BYT MSR with wrmsrl_on_cpu()

commit 0dd23f94251f49da99a6cbfb22418b2d757d77d6 upstream.

Commit 007bea098b86 (intel_pstate: Add setting voltage value for
baytrail P states.) introduced byt_set_pstate() with the assumption that
it would always be run by the CPU whose MSR is to be written by it.  It
turns out, however, that is not always the case in practice, so modify
byt_set_pstate() to enforce the MSR write done by it to always happen on
the right CPU.

Fixes: 007bea098b86 (intel_pstate: Add setting voltage value for baytrail P states.)
Signed-off-by: Joe Konno <joe.konno at intel.com>
Acked-by: Kristen Carlson Accardi <kristen at linux.intel.com>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki at intel.com>
Signed-off-by: Kamal Mostafa <kamal at canonical.com>
---
 drivers/cpufreq/intel_pstate.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/cpufreq/intel_pstate.c b/drivers/cpufreq/intel_pstate.c
index 742eefb..c37c895 100644
--- a/drivers/cpufreq/intel_pstate.c
+++ b/drivers/cpufreq/intel_pstate.c
@@ -497,7 +497,7 @@ static void byt_set_pstate(struct cpudata *cpudata, int pstate)

 	val |= vid;

-	wrmsrl(MSR_IA32_PERF_CTL, val);
+	wrmsrl_on_cpu(cpudata->cpu, MSR_IA32_PERF_CTL, val);
 }

 #define BYT_BCLK_FREQS 5
--
1.9.1