[3.19.y-ckt stable] Patch "arm64: KVM: Add workaround for Cortex-A57 erratum 834220" has been added to staging queue

[Kamal Mostafa]

On Tue, 2015-12-15 at 13:24 -0800, Kamal Mostafa wrote:
> This is a note to let you know that I have just added a patch titled
> 
>     arm64: KVM: Add workaround for Cortex-A57 erratum 834220
> 
> to the linux-3.19.y-queue branch of the 3.19.y-ckt extended stable tree 
> which can be found at:
> 
>     http://kernel.ubuntu.com/git/ubuntu/linux.git/log/?h=linux-3.19.y-queue
> 
> This patch is scheduled to be released in version 3.19.8-ckt12.

Oops, not suitable for 3.19-stable (no "alternative_if_not" in 3.19).
Dropping from the 3.19-stable queue, and sorry for the noise.

 -Kamal


> If you, or anyone else, feels it should not be added to this tree, please 
> reply to this email.
> 
> For more information about the 3.19.y-ckt tree, see
> https://wiki.ubuntu.com/Kernel/Dev/ExtendedStable
> 
> Thanks.
> -Kamal
> 
> ------
> 
> From fcf70c81f42f39a6b0120bc7e713dd2d337c6449 Mon Sep 17 00:00:00 2001
> From: Marc Zyngier <marc.zyngier at arm.com>
> Date: Mon, 16 Nov 2015 10:28:18 +0000
> Subject: arm64: KVM: Add workaround for Cortex-A57 erratum 834220
> 
> commit 498cd5c32be6e32bc0f8efcad48ab094bb2bfdf3 upstream.
> 
> Cortex-A57 parts up to r1p2 can misreport Stage 2 translation faults
> when a Stage 1 permission fault or device alignment fault should
> have been reported.
> 
> This patch implements the workaround (which is to validate that the
> Stage-1 translation actually succeeds) by using code patching.
> 
> Reviewed-by: Will Deacon <will.deacon at arm.com>
> Signed-off-by: Marc Zyngier <marc.zyngier at arm.com>
> Signed-off-by: Christoffer Dall <christoffer.dall at linaro.org>
> [ kamal: backport to 3.19-stable: context ]
> Signed-off-by: Kamal Mostafa <kamal at canonical.com>
> ---
>  arch/arm64/Kconfig                  | 21 +++++++++++++++++++++
>  arch/arm64/include/asm/cpufeature.h |  3 ++-
>  arch/arm64/kernel/cpu_errata.c      |  9 +++++++++
>  arch/arm64/kvm/hyp.S                |  6 ++++++
>  4 files changed, 38 insertions(+), 1 deletion(-)
> 
> diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
> index 67f5ba5..128ea92 100644
> --- a/arch/arm64/Kconfig
> +++ b/arch/arm64/Kconfig
> @@ -310,6 +310,27 @@ config ARM64_ERRATUM_832075
> 
>  	  If unsure, say Y.
> 
> +config ARM64_ERRATUM_834220
> +	bool "Cortex-A57: 834220: Stage 2 translation fault might be incorrectly reported in presence of a Stage 1 fault"
> +	depends on KVM
> +	default y
> +	help
> +	  This option adds an alternative code sequence to work around ARM
> +	  erratum 834220 on Cortex-A57 parts up to r1p2.
> +
> +	  Affected Cortex-A57 parts might report a Stage 2 translation
> +	  fault as the result of a Stage 1 fault for load crossing a
> +	  page boundary when there is a permission or device memory
> +	  alignment fault at Stage 1 and a translation fault at Stage 2.
> +
> +	  The workaround is to verify that the Stage 1 translation
> +	  doesn't generate a fault before handling the Stage 2 fault.
> +	  Please note that this does not necessarily enable the workaround,
> +	  as it depends on the alternative framework, which will only patch
> +	  the kernel if an affected CPU is detected.
> +
> +	  If unsure, say Y.
> +
>  config ARM64_ERRATUM_845719
>  	bool "Cortex-A53: 845719: a load might read incorrect data"
>  	depends on COMPAT
> diff --git a/arch/arm64/include/asm/cpufeature.h b/arch/arm64/include/asm/cpufeature.h
> index 5fe4bef..8a90489 100644
> --- a/arch/arm64/include/asm/cpufeature.h
> +++ b/arch/arm64/include/asm/cpufeature.h
> @@ -24,8 +24,9 @@
>  #define ARM64_WORKAROUND_CLEAN_CACHE		0
>  #define ARM64_WORKAROUND_DEVICE_LOAD_ACQUIRE	1
>  #define ARM64_WORKAROUND_845719			2
> +#define ARM64_WORKAROUND_834220			3
> 
> -#define ARM64_NCAPS				3
> +#define ARM64_NCAPS				4
> 
>  #ifndef __ASSEMBLY__
> 
> diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c
> index ad6d523..40fe97e 100644
> --- a/arch/arm64/kernel/cpu_errata.c
> +++ b/arch/arm64/kernel/cpu_errata.c
> @@ -92,6 +92,15 @@ struct arm64_cpu_capabilities arm64_errata[] = {
>  			   (1 << MIDR_VARIANT_SHIFT) | 2),
>  	},
>  #endif
> +#ifdef CONFIG_ARM64_ERRATUM_834220
> +	{
> +	/* Cortex-A57 r0p0 - r1p2 */
> +		.desc = "ARM erratum 834220",
> +		.capability = ARM64_WORKAROUND_834220,
> +		MIDR_RANGE(MIDR_CORTEX_A57, 0x00,
> +			   (1 << MIDR_VARIANT_SHIFT) | 2),
> +	},
> +#endif
>  #ifdef CONFIG_ARM64_ERRATUM_845719
>  	{
>  	/* Cortex-A53 r0p[01234] */
> diff --git a/arch/arm64/kvm/hyp.S b/arch/arm64/kvm/hyp.S
> index 0a2ff0f..8fc281c 100644
> --- a/arch/arm64/kvm/hyp.S
> +++ b/arch/arm64/kvm/hyp.S
> @@ -1187,9 +1187,15 @@ el1_trap:
>  	b.ne	1f		// Not an abort we care about
> 
>  	/* This is an abort. Check for permission fault */
> +alternative_if_not ARM64_WORKAROUND_834220
>  	and	x2, x1, #ESR_EL2_FSC_TYPE
>  	cmp	x2, #FSC_PERM
>  	b.ne	1f		// Not a permission fault
> +alternative_else
> +	nop			// Use the permission fault path to
> +	nop			// check for a valid S1 translation,
> +	nop			// regardless of the ESR value.
> +alternative_endif
> 
>  	/*
>  	 * Check for Stage-1 page table walk, which is guaranteed
> --
> 1.9.1
>