[PATCH trusty SRU 4/4] arm64: add APM X-Gene SoC RTC DTS entry

[Ming Lei]

From: Loc Ho <lho at apm.com>

This patch adds APM X-Gene SoC RTC DTS entry

Signed-off-by: Rameshwar Prasad Sahu <rsahu at apm.com>
Signed-off-by: Loc Ho <lho at apm.com>
Cc: Jon Masters <jcm at redhat.com>
Cc: Alessandro Zummo <a.zummo at towertech.it>
Cc: Catalin Marinas <catalin.marinas at arm.com>
Cc: Will Deacon <will.deacon at arm.com>
Signed-off-by: Andrew Morton <akpm at linux-foundation.org>
(cherry picked from commit 364b92106a57025d01e70dbace3b5ef076724ed0)
Signed-off-by: Ming Lei <ming.lei at canonical.com>
---
 arch/arm64/boot/dts/apm-storm.dtsi |   21 +++++++++++++++++++++
 1 file changed, 21 insertions(+)

diff --git a/arch/arm64/boot/dts/apm-storm.dtsi b/arch/arm64/boot/dts/apm-storm.dtsi
index 8a0f9e1..1b25dd4 100644
--- a/arch/arm64/boot/dts/apm-storm.dtsi
+++ b/arch/arm64/boot/dts/apm-storm.dtsi
@@ -317,6 +317,19 @@
 				reg-names = "csr-reg";
 				clock-output-names = "pcie4clk";
 			};
+
+			rtcclk: rtcclk at 17000000 {
+				compatible = "apm,xgene-device-clock";
+				#clock-cells = <1>;
+				clocks = <&socplldiv2 0>;
+				reg = <0x0 0x17000000 0x0 0x2000>;
+				reg-names = "csr-reg";
+				csr-offset = <0xc>;
+				csr-mask = <0x2>;
+				enable-offset = <0x10>;
+				enable-mask = <0x2>;
+				clock-output-names = "rtcclk";
+			};
 		};
 
                 msi: msi at 79000000 {
@@ -579,5 +592,13 @@
 			phyid = <3>;
 			phy-mode = "rgmii";
 		};
+
+		rtc: rtc at 10510000 {
+			compatible = "apm,xgene-rtc";
+			reg = <0x0 0x10510000 0x0 0x400>;
+			interrupts = <0x0 0x46 0x4>;
+			#clock-cells = <1>;
+			clocks = <&rtcclk 0>;
+		};
 	};
 };
-- 
1.7.9.5