[3.5.y.z extended stable] Patch "ARM: sa11x0/assabet: ensure CS2 is configured appropriately" has been added to staging queue

Luis Henriques luis.henriques at canonical.com
Fri Nov 29 14:02:12 UTC 2013

This is a note to let you know that I have just added a patch titled

    ARM: sa11x0/assabet: ensure CS2 is configured appropriately

to the linux-3.5.y-queue branch of the 3.5.y.z extended stable tree 
which can be found at:


If you, or anyone else, feels it should not be added to this tree, please 
reply to this email.

For more information about the 3.5.y.z tree, see



>From 5fb9aa831380d9c67d90eb4fe4cbf35c1465aabf Mon Sep 17 00:00:00 2001
From: Russell King <rmk+kernel at arm.linux.org.uk>
Date: Wed, 16 Oct 2013 00:09:02 +0100
Subject: ARM: sa11x0/assabet: ensure CS2 is configured appropriately

commit f3964fe1c9d9a887d65faf594669852e4dec46e0 upstream.

The CS2 region contains the Assabet board configuration and status
registers, which are 32-bit.  Unfortunately, some boot loaders do not
configure this region correctly, leaving it setup as a 16-bit region.
Fix this.

Signed-off-by: Russell King <rmk+kernel at arm.linux.org.uk>
Signed-off-by: Luis Henriques <luis.henriques at canonical.com>
 arch/arm/mach-sa1100/assabet.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/arch/arm/mach-sa1100/assabet.c b/arch/arm/mach-sa1100/assabet.c
index d1dc7f1..3417058 100644
--- a/arch/arm/mach-sa1100/assabet.c
+++ b/arch/arm/mach-sa1100/assabet.c
@@ -509,6 +509,9 @@ static void __init assabet_map_io(void)
 	 * Its called GPCLKR0 in my SA1110 manual.
 	Ser1SDCR0 |= SDCR0_SUS;
+	MSC1 = (MSC1 & ~0xffff) |
+		MSC_NonBrst | MSC_32BitStMem |
+		MSC_RdAcc(2) | MSC_WrAcc(2) | MSC_Rec(0);

 	if (!machine_has_neponset())

More information about the kernel-team mailing list