[PATCH 117/118] Revert "drm/i915: GFX_MODE Flush TLB Invalidate Mode must be '1' for scanline waits"

[Luis Henriques]

3.5.7.12 -stable review patch.  If anyone has any objections, please let me know.

------------------

From: Luis Henriques <luis.henriques at canonical.com>

This reverts commit 899b5509abbdfee2eab408e7178e559346091ad3, which is commit
f05bb0c7b624252a5e768287e340e8e45df96e42 in Linus' tree.

This commit has been shown to cause GPU hangs on Sandy Bridge GPUs

BugLink: http://bugs.launchpad.net/bugs/1140716

Signed-off-by: Steve Conklin <sconklin at canonical.com>
Acked-by: Brad Figg <brad.figg at canonical.com>
Acked-by: Luis Henriques <luis.henriques at canonical.com>
Cc: Chris Wilson <chris at chris-wilson.co.uk>
Cc: Ben Widawsky <ben at bwidawsk.net>
Cc: Daniel Vetter <daniel.vetter at ffwll.ch>
Signed-off-by: Luis Henriques <luis.henriques at canonical.com>
---
 drivers/gpu/drm/i915/intel_ringbuffer.c | 5 -----
 1 file changed, 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index e75d794..78486c7 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -421,11 +421,6 @@ static int init_render_ring(struct intel_ring_buffer *ring)
 	if (INTEL_INFO(dev)->gen >= 6)
 		I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE));
 
-	/* Required for the hardware to program scanline values for waiting */
-	if (INTEL_INFO(dev)->gen == 6)
-		I915_WRITE(GFX_MODE,
-			   _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_ALWAYS));
-
 	if (IS_GEN7(dev))
 		I915_WRITE(GFX_MODE_GEN7,
 			   _MASKED_BIT_DISABLE(GFX_TLB_INVALIDATE_ALWAYS) |
-- 
1.8.1.2